Obtaining debug information from a flash memory device

• US 8,966,319 B2
• Filed: 02/22/2011
• Issued: 02/24/2015
• Est. Priority Date: 02/22/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Fai, Anthony, Wakrat, Nir Jacob, Seroff, Nicholas
• Primary Examiner(s): Riad, Amine
• Application Number:
  US13/032,541
• Publication Number:
  US 20120216079A1
• Time in Patent Office: 1,463 Days
• Field of Search: 714/42
• US Class Current: 714/42
• CPC Class Codes: G06F 11/362 Software debugging

Abstract

This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.

Claims

1. A method comprising:

receiving, from a host through a host interface of a memory device, a first command instructing the memory device to obtain debug information associated with the memory device, wherein the memory device includes non-volatile memory;

wherein the debug information includes information identifying one or more memory operations performed by the memory device, and information identifying a portion of the memory device in which an error occurred during the memory operations;

storing, by the memory device, the collected debug information in response to the received command;

collecting, by a memory controller of the memory device, the debug information during operation of the memory device in response to receiving the command;

receiving, from the host through the host interface, a second command to provide the host with at least the portion of the collected debug information; and

providing at least a portion of the collected debug information to the host through the host interface in response to the received request.

2. The method of claim 1, further comprising, based on the received first command, setting one or more triggers that the memory controller uses to determine when to collect the debug information during operation of the memory device.

3. The method of claim 2, wherein the one or more triggers include a trigger to collect the debug information during memory operations pertaining to one or more memory addresses.

4. The method of claim 3, wherein the one or more memory addresses are associated with a page of the non-volatile memory, and wherein the first trigger causes the collected debug information to be associated with the page.

5. The method of claim 2, wherein the one or more triggers include a trigger to collect the debug information in association with one or more of a failed read operation, failed program operation, and a failed erase operation on the non-volatile memory.

6. The method of claim 2, wherein the one or more triggers include a trigger to collect the debug information in response to an instruction to perform a memory operation on a memory address that is invalid for the non-volatile memory.

7. The method of claim 2, wherein the one or more triggers are defined in the received command or by the host.

8. The method of claim 2, wherein the one or more triggers each include a set of criteria that describe one or more states of the memory device.

9. The method of claim 1, wherein the collected debug information includes information identifying one or more memory addresses to which the collected debug information pertains, and wherein the portion of the collected debug information requested in the second command includes debug information pertaining to one or more memory addresses.

10. The method of claim 1, wherein the debug information is provided to the host as the debug information is collected by the memory controller.

11. The method of claim 1, wherein the debug information includes information identifying one or more memory operations performed by the memory device, and information identifying a portion of the memory device in which an error occurred during the memory operations.

12. A method comprising:

transmitting, by a host, a first command to a memory device that includes a memory controller and non-volatile memory, wherein the first command instructs the memory device to collect and store debug information associated with the memory device;

transmitting, by the host, a second command to provide the host with at least a portion of the collected debug information;

receiving, at the host, at least a portion of the debug information collected by the memory device in response to the second command; and

performing, by the host, one or more operations in response to the received debug information.

13. The method of claim 12, wherein the first command includes trigger information identifying one or more triggers that the memory controller uses to determine when to collect the debug information during operation of the memory device.

14. The method of claim 13, wherein the trigger information includes one or more of a register value to be programmed to a register of the memory device, and instructions to be programmed to volatile memory of the memory device.

15. The method of claim 12, wherein performing the one or more operations includes performing an operation that causes at least a portion of the memory device to be reset.

16. A memory device comprising:

non-volatile memory;

a host interface that communicatively connects the memory device to a host; and

a memory controller that is configured to perform memory operations on the non-volatile memory and that communicates with the host through the host interface, wherein the memory controller is further configured to;

receive, from the host through the host interface, a first command to obtain debug information associated with the memory device and the non-volatile memory;

collect debug information stored by the memory device during operation of the memory device in response to receiving the first command;

receive, from the host through the host interface, a second command to provide the host with at least the portion of the collected debug information; and

provide at least a portion of the collected debug information to the host through the host interface in response to the received request.

17. The memory device of claim 16, wherein the memory controller is further configured to set one or more triggers that the memory controller uses to determine when to collect the debug information during operation of the memory device.

18. The memory device of claim 17, wherein the one or more triggers include a trigger to collect the debug information during memory operations pertaining to one or more memory addresses.

19. The memory device of claim 17, wherein the one or more triggers include a trigger to collect the debug information in association with one or more of a failed read operation, failed program operation, and a failed erase operation on the non-volatile memory.

20. The memory device of claim 17, wherein the one or more triggers include a trigger to collect the debug information in association with a received or generated instruction to perform a memory operation pertaining to a memory address that is invalid with regard to the non-volatile memory.

21. The memory device of claim 16, wherein the non-volatile memory includes one or more flash memory dies.

22. A system comprising:

non-volatile memory; and

a memory controller that is configured to perform memory operations on the non-volatile memory and that communicates with a host through a host interface, wherein the memory controller is further configured to;

receive, from the host through the host interface, a first command to obtain debug information associated with the memory device and the non-volatile memory;

collect debug information stored by the memory device during operation of the memory device in response to receiving the first command; and

receive, from the host through the host interface, a second command to provide the host with at least the portion of the collected debug information; and

provide at least a portion of the collected debug information to the host through the host interface in response to the received request.

23. The system of claim 22, wherein the memory controller is further configured to set one or more triggers that the memory controller uses to determine when to collect the debug information during operation of the memory device.

24. The system of claim 23, wherein the one or more triggers include a trigger to collect the debug information during memory operations pertaining to one or more memory addresses.

25. The system of claim 23, wherein the one or more triggers include a trigger to collect the debug information in association with one or more of a failed read operation, failed program operation, and a failed erase operation on the non-volatile memory.

26. The system of claim 23, wherein the one or more triggers include a trigger to collect the debug information in association with a received or generated instruction to perform a memory operation pertaining to a memory address that is invalid with regard to the non-volatile memory.