Selective error correction in memory to reduce power consumption

• US 8,966,345 B2
• Filed: 11/28/2012
• Issued: 02/24/2015
• Est. Priority Date: 11/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wilkerson, Christopher B., Alameldeen, Alaa R., Lu, Shih-Lien L.
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/688,028
• Publication Number:
  US 20140149822A1
• Time in Patent Office: 818 Days
• Field of Search: 714/774, 714/769, 714/758, 714/764, 714/748, 714/805, 714/762, 714/752
• US Class Current: 714/774
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction

Abstract

Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.

Claims

1. An apparatus, comprising:

an error correction block configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory; and

a control block coupled to the error correction block and configured to selectively enable the error correction block to perform error correction on data read from the memory or disable the error correction block from performance of error correction on data read from the memory, based at least in part on a current operation mode of the memory.

2. The apparatus of claim 1, further comprising a memory controller, wherein the memory controller comprises the error correction block and the control block.

3. The apparatus of claim 2, further comprising one or more processors coupled with the memory controller.

4. The apparatus of claim 1, wherein the control block is configured to determine whether, since a most recent transition of the memory to a first operation mode in which the memory has a first susceptibility for error from a second operation mode in which the memory has a second susceptibility for error that is greater than the first susceptibility, error correction has been performed on the data read from the first portion of the memory.

5. The apparatus of claim 4, wherein the control block is configured to enable the error correction block to perform error correction on the data read from the first portion, responsive to a determination that, since the most recent transition, error correction has not been performed on data read from the first portion.

6. The apparatus of claim 4, wherein the control block is configured to disable the error correction block from performance of error correction on the data read from the first portion, responsive to a determination that, since the most recent transition, error correction has been performed on data stored in the first portion.

7. The apparatus of claim 6, wherein the control block is configured to disable the error correction block at least until the memory transitions from the first operation mode back to the second operation mode.

8. The apparatus of claim 4, wherein the second portion is configured to store an indication of whether, since the most recent transition, error correction has been performed on data read from the first portion, wherein the control block is further configured to write or cause to write, to the second portion, the indication that, since the most recent transition, error correction has been performed on data read from the first portion, responsive to the performed error correction.

9. The apparatus of claim 2, further comprising the memory, wherein the memory is configured to be refreshed at a first rate while in a first operation mode and refreshed at a second rate while in a second operation mode, and wherein the second rate is lower than the first rate.

10. The apparatus of claim 9, wherein the memory consumes less power while in the first operation mode than in the second operation mode.

11. The apparatus of claim 1, wherein the error correction block is further configured to calculate and store, in the second portion of the memory, the error correction code that corresponds to the data read from the first portion of the memory;

and

the control block is further configured to selectively enable the error correction block to calculate and store the error correction code or disable the error correction block from calculation and storage of the error correction code, based at least in part on the current operation mode of the memory.

12. The apparatus of claim 11, wherein the control block is further configured to transition the memory from a first operation mode in which the memory has a first susceptibility to error to a second operation mode in which the memory has a second susceptibility to error that is greater than the first susceptibility.

13. The apparatus of claim 12, wherein the transition comprises determination of whether the error correction code stored in the second portion is valid for data read from the first portion.

14. The apparatus of claim 13, wherein the control block is further configured to enable the error correction block to perform the calculation and storage, responsive to a determination that the error correction code is invalid.

15. The apparatus of claim 12, wherein on transition of the memory from the second operation mode to the first operation mode, the control block is configured to disable the error correction block from calculation and storage of the error correction code until transition of the memory from the first operation mode back to the second operation mode.

16. The apparatus of claim 15, wherein the control block is configured to designate the error correction code as invalid responsive to a first write to the second portion after transition from the second operation mode to the first operation mode.

17. The apparatus of claim 1, wherein the memory comprises volatile memory.

18. A system comprising:

an error correction block configured to;

perform error correction on data read from a first portion of memory based on a corresponding error correction code read from a second portion of the memory; and

calculate and store, in the second portion of the memory, the error correction code based on the data read from the first portion of the memory,

a control block coupled to the error correction block and configured to;

selectively enable the error correction block to perform error correction on data read from the memory or disable the error correction block from performance of error correction on data read from the memory, based at least in part on a current operation mode of memory; and

selectively enable the error correction block to calculate and store the error correction code or disable the error correction block from calculation and storage of the error correction code, based at least in part on the current operation mode of the memory, and

a touch screen display.

19. A computer-implemented method, comprising:

determining whether, by a control block of a memory controller, since a most recent transition of memory to a first operation mode in which the memory has a first susceptibility for error from a second operation mode in which the memory has a second susceptibility for error that is greater than the first susceptibility, error correction has been performed on data read from a first portion of the memory; and

selectively performing, by an error correction block of the memory controller under control of the control block, error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, based on the determination.

20. The computer-implemented method of claim 19, further comprising performing, by the error correction block under control of the control block, error correction on the data read from the first portion, responsive to a determination that, since the most recent transition, error correction has not been performed on data read from the first portion.

21. The computer-implemented method of claim 19, further comprising refraining, by the error correction block under control of the control block, from performance of error correction on the data read from the first portion, responsive to a determination that, since the most recent transition, error correction has been performed on data stored in the first portion.

22. The computer-implemented method of claim 21, wherein the refraining comprises refraining from performance of the error correction at least until the memory transitions from the first operation mode back to the second operation mode.

23. The computer-implemented method of claim 19, wherein the second portion is configured to store an indication of whether, since the most recent transition, error correction has been performed on data read from the first portion, the method further comprising writing or causing to write, to the second portion, the indication that, since the most recent transition, error correction has been performed on data read from the first portion, responsive to the performed error correction.