Systems and methods for integrated circuit C4 ball placement
First Claim
Patent Images
1. A method of laying out C4 ball placements, comprising using a computer to perform the following steps:
- (i) calculating optimal position of C4 solder balls on a chip using a quadratic optimization technique;
(ii) producing a grid map of all possible C4 ball locations based on a minimum pitch distance for the C4 balls and a length and width of the chip;
(iii) generating a temperature map from the produced grid map;
(iv) determining thermal stress on a C4 ball at each possible C4 ball location in the grid map by using the temperature map;
(v) calculating a thermal failure rate for each possible C4 ball location based on thermal stresses, creep rates, and number of cycles to failure rates for the C4 balls;
(vi) producing a reduced grid map by removing all possible C4 ball locations from the grid map that have a higher thermal failure rate than a predetermined threshold;
(vii) legalizing possible C4 ball locations in the reduced grid map so as to generate bin entries;
(viii) sorting possible C4 ball locations based on bin entries; and
(ix) locating a set of C4 ball locations within the reduced grid map using bin entries such that overlaps between other C4 ball locations and removed C4 ball locations are avoided.
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Abstract
Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling.
33 Citations
10 Claims
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1. A method of laying out C4 ball placements, comprising using a computer to perform the following steps:
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(i) calculating optimal position of C4 solder balls on a chip using a quadratic optimization technique; (ii) producing a grid map of all possible C4 ball locations based on a minimum pitch distance for the C4 balls and a length and width of the chip; (iii) generating a temperature map from the produced grid map; (iv) determining thermal stress on a C4 ball at each possible C4 ball location in the grid map by using the temperature map; (v) calculating a thermal failure rate for each possible C4 ball location based on thermal stresses, creep rates, and number of cycles to failure rates for the C4 balls; (vi) producing a reduced grid map by removing all possible C4 ball locations from the grid map that have a higher thermal failure rate than a predetermined threshold; (vii) legalizing possible C4 ball locations in the reduced grid map so as to generate bin entries; (viii) sorting possible C4 ball locations based on bin entries; and (ix) locating a set of C4 ball locations within the reduced grid map using bin entries such that overlaps between other C4 ball locations and removed C4 ball locations are avoided. - View Dependent Claims (2, 3, 4, 5)
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6. A method for laying out C4 ball placements, the method comprising using a computer to perform the following steps:
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(i) inputting into the computer specifications regarding a length and width of a semiconductor device to receive C4 balls; (ii) inputting into the computer a device netlist having a number of electrical contacts to be implemented; (iii) inputting into the computer a minimum number of cycles to failure for C4 solder balls; (iv) operating the computer to calculate an optimal position of C4 solder balls using a quadratic optimization technique; (v) generating a grid map of all possible C4 ball locations based on a minimum pitch distance for the C4 balls and the length and width of the semiconductor device; (vi) generating a temperature map from the generated grid map; (vii) operating the computer to calculate the thermal stress on a C4 ball at each possible C4 ball location in the grid maps by using the temperature map; (viii) operating the computer to calculate a thermal failure rate for each possible C4 ball location based on thermal stresses, creep rates, and number of cycles to failure rates for the C4 balls; (ix) generating a reduced grid map by removing all possible C4 ball locations from the grid map that have a higher thermal failure rate than a predetermined threshold; (x) computationally legalizing possible C4 ball locations in the reduced grid map so as to generate bin entries; (xi) sorting possible C4 ball locations based on bin entries; and (xii) using the computer to locate a set of C4 ball locations on the semiconductor device and within the reduced grid map using bin entries such that overlaps between other C4 ball locations and removed C4 ball locations are avoided. - View Dependent Claims (7, 8, 9, 10)
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Specification