Semiconductor device and method for manufacturing the same

• US 8,968,017 B2
• Filed: 09/11/2013
• Issued: 03/03/2015
• Est. Priority Date: 03/22/2013
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawamura, Keiko, Kobayashi, Hitoshi, Kawaguchi, Yusuke, Katoh, Shunsuke
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US14/024,141
• Publication Number:
  US 20140284707A1
• Time in Patent Office: 538 Days
• Field of Search: 257/330, 438/270
• US Class Current: 439/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

According to one embodiment, a semiconductor memory device includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer is a first conductivity type. The second semiconductor layer is provided in a surface region of the first semiconductor layer and is the first conductivity type. The first electrode is provided inside a first trench extending in the first direction and opened to a surface of the second semiconductor layer. The second electrode is provided in a second trench extending in a second direction crossing the first direction and opened to the surface of the second semiconductor layer. A dimension from the surface of the second semiconductor layer to a lower end of the second electrode is shorter than a dimension from the surface of the second semiconductor layer to a lower end of the first electrode.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of the first conductivity type provided in a surface region of the first semiconductor layer;

a first electrode extending in a first direction and provided inside a first trench, the first trench extending in the first direction and being opened to a surface of the second semiconductor layer; and

a second electrode extending in a second direction crossing the first direction, and provided in a second trench, the second trench extending in the second direction and being opened to the surface of the second semiconductor layer, a dimension from the surface of the second semiconductor layer to a lower end of the second electrode being shorter than a dimension from the surface of the second semiconductor layer to a lower end of the first electrode.

2. The device according to claim 1, wherein the first electrode is provided in a plurality with a prescribed spacing.

3. The device according to claim 1, wherein the second electrode is provided in a plurality with a prescribed spacing.

4. The device according to claim 1, wherein an upper end of the first electrode is exposed to the surface of the second semiconductor layer.

5. The device according to claim 1, further comprising:

a third electrode provided on the second semiconductor layer and electrically connected to the first electrode.

6. The device according to claim 1, further comprising:

an insulating film provided inside the first trench and covering a side surface and a lower surface of the first electrode.

7. The device according to claim 1, further comprising:

an insulating film provided inside the second trench and covering the second electrode.

8. The device according to claim 1, wherein an impurity concentration of the second semiconductor layer is higher than an impurity concentration of the first semiconductor layer.

9. The device according to claim 1, wherein an impurity concentration of the first semiconductor layer is 1×

10¹⁷ cm<sup>−

3</sup> or less.

10. The device according to claim 1, wherein an impurity concentration of the second semiconductor layer is 1×

10¹⁹ cm<sup>−

3</sup> or more.

11. The device according to claim 1, further comprising:

a third semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second semiconductor layer.

12. The device according to claim 1, further comprising:

an insulating film provided inside the first trench and covering the first electrode.