Fin structure with varying isolation thickness

• US 8,969,155 B2
• Filed: 05/10/2013
• Issued: 03/03/2015
• Est. Priority Date: 05/10/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Rim, Kern
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US13/891,212
• Publication Number:
  US 20140332861A1
• Time in Patent Office: 662 Days
• Field of Search: 438/268, 438/297, 438/425, 438/595, 257/302, 257/347, 257/349, 257/350, 257/368, 257/401, 257/E21.618, 257/E21.628, 257/E21.654, 257/E29.255
• US Class Current: 438/268
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different thicknesses.

Claims

1. A method of forming a semiconductor structure comprising:

depositing a first nitride layer on a semiconductor structure comprising a first fin and a second fin;

removing a portion of the first nitride layer to form nitride spacer regions on a lower sidewall portion of the first fin and a lower sidewall portion of the second fin;

removing the nitride spacer regions from the first fin;

depositing an oxide region on the semiconductor structure;

recessing the oxide region;

depositing a second nitride layer over the semiconductor structure;

removing a portion of the second nitride layer to form nitride spacer regions on an upper sidewall portion of the first fin and an upper sidewall portion of the second fin;

forming an isolation region under the first fin by performing a thermal oxidation; and

removing the nitride spacer regions from the upper sidewall portion of the first fin and the upper sidewall portion of the second fin.

2. The method of claim 1, further comprising planarizing the oxide region prior to recessing the oxide region.

3. The method of claim 2, wherein planarizing the oxide region is performed via a chemical mechanical polish process.

4. The method of claim 1, wherein depositing a first nitride layer is performed via a chemical vapor deposition process.

5. The method of claim 4, wherein depositing a first nitride layer comprises depositing a nitride layer having a thickness ranging from about 3 nanometers to about 10 nanometers.

6. The method of claim 1, wherein recessing the oxide region comprises recessing the oxide region to a level below the top of the first fin and second fin, and above the nitride spacer regions on the lower sidewall portion of the second fin.

7. The method of claim 1, wherein removing a portion of the first nitride layer is performed by a reactive ion etch process.

8. The method of claim 1, wherein performing a thermal oxidation comprises performing a thermal oxidation at a temperature ranging from about 900 degrees Celsius to about 1300 degrees Celsius.

9. The method of claim 1, further comprising depositing a mask region on the second fin prior to removing the nitride spacer regions from the first fin.

10. The method of claim 9, wherein depositing a mask region comprises depositing photoresist.

11. The method of claim 9, wherein depositing a mask region comprises depositing an oxide hard mask.

12. A method of forming a semiconductor structure comprising:

depositing a first nitride layer on a semiconductor structure comprising a first fin and a second fin;

removing a portion of the first nitride layer to form nitride spacer regions on a lower sidewall portion of the first fin and a lower sidewall portion of the second fin;

removing the nitride spacer regions from the first fin;

depositing a first oxide region on the semiconductor structure;

recessing the first oxide region to a level below the top of the first fin and second fin, and above the nitride spacer regions on the lower sidewall portion of the second fin;

depositing a second nitride layer over the semiconductor structure;

removing a portion of the second nitride layer to form nitride spacer regions on an upper sidewall portion of the first fin and an upper sidewall portion of the second fin;

depositing a second oxide region on the semiconductor structure;

forming an isolation region under the first fin and under the second fin by performing a thermal oxidation;

removing the second oxide region from the semiconductor structure; and

removing the nitride spacer regions from the upper sidewall portion of the first fin and the upper sidewall portion of the second fin.

13. The method of claim 12, wherein removing a portion of the first nitride layer is performed by a reactive ion etch process.

14. The method of claim 12, wherein performing a thermal oxidation comprises performing a thermal oxidation at a temperature ranging from about 900 degrees Celsius to about 1300 degrees Celsius.

15. The method of claim 12, further comprising depositing a mask region on the second fin prior to removing the nitride spacer regions from the first fin.

16. A semiconductor structure, comprising:

a semiconductor substrate;

a first fin formed in the semiconductor substrate;

a second fin formed in the semiconductor substrate;

wherein a first oxide region is disposed below the first fin; and

wherein a second oxide region is disposed below the second fin; and

wherein the first oxide region is thicker than the second oxide region;

a fin portion disposed below the second oxide region, wherein the fin portion is in direct physical contact with the semiconductor substrate;

nitride spacers disposed adjacent to the fin portion.

17. The semiconductor structure of claim 16, wherein the first oxide region is about four to five times thicker than the second oxide region.

18. The semiconductor structure of claim 16, wherein the first oxide region has a thickness ranging from about 50 nanometers to about 200 nanometers, and wherein the second oxide region has a thickness ranging from about 10 nanometers to about 50 nanometers.