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Vertical gate LDMOS device

  • US 8,969,158 B2
  • Filed: 01/28/2014
  • Issued: 03/03/2015
  • Est. Priority Date: 08/11/2011
  • Status: Active Grant
First Claim
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1. A method of fabricating a vertical gate region in a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

  • depositing a masking layer over an area defined on a well region implanted on a substrate;

    etching through the masking layer in a first portion of the area to expose the well region;

    etching the exposed well region to form a first trench;

    filling the first trench with a dielectric material;

    etching through the masking layer in a second portion of the area to expose the well region;

    forming a second trench in the well such that the second trench abuts the first trench; and

    forming an asymmetric vertical gate of the LDMOS transistor by filling the second trench with a conductive material.

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