Vertical gate LDMOS device

• US 8,969,158 B2
• Filed: 01/28/2014
• Issued: 03/03/2015
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Zuniga, Marco A., Lu, Yang, Fatemizadeh, Badredin, Prasad, Jayasimha, Paul, Amit, Ruan, Jun
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US14/166,659
• Publication Number:
  US 20140147979A1
• Time in Patent Office: 399 Days
• Field of Search: 438/270, 438/286, 438/589, 438/FOR.190
• US Class Current: 438/270
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.

Claims

1. A method of fabricating a vertical gate region in a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

depositing a masking layer over an area defined on a well region implanted on a substrate;

etching through the masking layer in a first portion of the area to expose the well region;

etching the exposed well region to form a first trench;

filling the first trench with a dielectric material;

etching through the masking layer in a second portion of the area to expose the well region;

forming a second trench in the well such that the second trench abuts the first trench; and

forming an asymmetric vertical gate of the LDMOS transistor by filling the second trench with a conductive material.

2. The method of claim 1, further comprising forming a region of the dielectric material adjacent to a bottom of the second trench prior to filling the second trench with the conductive material.

3. The method of claim 2 further comprising depositing a layer of nitride on a sidewall of the second trench prior to forming the region of the dielectric material adjacent to the bottom of the second trench, wherein the sidewall abuts the well region.

4. The method of claim 2, wherein forming the region of the dielectric material comprises oxidizing the bottom of the second trench.

5. The method of claim 1, wherein the masking layer comprises a nitride.

6. The method of claim 1, wherein the etching through the masking layer leaves residual spacers.

7. The method of claim 6, further comprising removing at least one of the spacers.

8. The method of claim 1, wherein a width of the first trench is different from a width of the second trench.

9. The method of claim 1, further comprising forming at least a portion of p-body of the vertical LDMOS transistor after forming the first trench.

10. The method of claim 9, wherein forming the portion of the p-body comprises implanting a p-type material in the well region through the first trench using a first p-type implant beam.

11. The method of claim 10, further comprising neutralizing a portion of the implanted p-type material using an n-type implant beam, wherein energy of the n-type implant beam is less than the energy of the p-type implant beam.

12. The method of claim 1, further comprising implanting into a source region of the transistor, a p-body region.

13. The method of claim 12, further comprising:

implanting, into the source region of the transistor, an n+ region and a p+ region, in the p-body region; and

implanting, into a drain region of the transistor, an n+ region.

14. The method of claim 1, wherein the area is defined by patterning another masking layer deposited on the well region.

15. The method of claim 14, wherein the another masking layer comprises a conductive material.

16. The method of claim 15, wherein the conductive material is polysilicon.