Thin film transistor display panel

• US 8,969,872 B2
• Filed: 03/07/2013
• Issued: 03/03/2015
• Est. Priority Date: 10/16/2012
• Status: Active Grant

• Current Assignee: Kookmin University, Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Kookmin University, Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Ahn, Byung Du, Lim, Ji Hun, Lim, Jun Hyung, Kim, Dae Hwan, Kim, Jae Hyeong, Lee, Je Hun, Jung, Hyun Kwang
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US13/789,335
• Publication Number:
  US 20140103332A1
• Time in Patent Office: 726 Days
• Field of Search: 257/43
• US Class Current: 257/57
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Claims

1. A thin film transistor display panel, comprising:

a substrate;

a gate electrode positioned on the substrate;

a gate insulating layer positioned on the gate electrode;

a semiconductor layer positioned on the gate insulating layer and comprising a channel portion; and

a source electrode and a drain electrode positioned on the semiconductor layer and spaced apart from one another;

wherein a first portion of the semiconductor layer overlaps both the source electrode and the gate electrode, wherein a second portion of the semiconductor layer overlaps both the drain electrode and the gate electrode, wherein the first portion of the semiconductor layer comprises a hill portion that protrudes, and wherein a thickness of the first portion of the semiconductor layer at a first end of the source electrode is larger than a thickness of the second portion of the semiconductor layer at a first end of the drain electrode.

2. The thin film transistor display panel of claim 1, wherein the source electrode is positioned on the first portion of the semiconductor layer and exposes an edge of the hill portion.

3. The thin film transistor display panel of claim 2, wherein the channel portion is disposed between the source electrode and the drain electrode.

4. The thin film transistor display panel of claim 3, further comprising:

a passivation layer disposed over the source electrode and the drain electrode;

wherein a first portion of the passivation layer overlaps the first portion of the semiconductor layer and the first portion of the passivation layer is higher than a second portion of the passivation layer overlapping the second portion of the semiconductor layer.

5. The thin film transistor display panel of claim 4, wherein the passivation layer covers a portion of the semiconductor layer exposed between the source electrode and the drain electrode.

6. The thin film transistor display panel of claim 1, wherein the first end of the source electrode and the first end of the drain electrode are positioned between a second end of the source electrode and a second end of the drain electrode.

7. The thin film transistor display panel of claim 1, wherein the hill portion has a thickness equal to or more than about 20 nm and less than or equal to about 50 nm.

8. The thin film transistor display panel of claim 1, further comprising:

an etching prevention layer covering the channel portion of the semiconductor layer.

9. The thin film transistor display panel of claim 8, wherein:

the etching prevention layer overlaps the source electrode and the drain electrode at both edges of the etching prevention layer.

10. The thin film transistor display panel of claim 9, wherein:

the etching prevention layer overlaps the hill portion of the semiconductor layer.

11. The thin film transistor display panel of claim 10, wherein:

one edge of the etching prevention layer protrudes upwardly.

12. The thin film transistor display panel of claim 8, wherein:

an edge of the etching prevention layer is positioned between the hill portion and a terminal edge of the source electrode.

13. The thin film transistor display panel of claim 8, wherein:

when it is assumed that a thickness of the hill portion is a value obtained by subtracting the thickness of the second portion of the semiconductor layer from the thickness of the first portion of the semiconductor layer, the thickness of the hill portion is equal to or more than about 20 nm and equal to or less than about 50 nm.

14. The thin film transistor display panel of claim 13, wherein:

a width of a portion at which the one edge of the etching prevention layer overlaps the hill portion of the semiconductor layer is equal to or less than about 5 μ

m.

15. The thin film transistor display panel of claim 14, wherein:

a width of a portion at which the edge of the source electrode overlaps the one edge of the etching prevention layer is equal to or less than about 7.5 μ

m.

16. The thin film transistor display panel of claim 15, wherein:

the source electrode is positioned on the first portion of the semiconductor layer and exposes the hill portion.

17. The thin film transistor display panel of claim 1, wherein:

the semiconductor layer comprises a semiconductive oxide.

18. The thin film transistor display panel of claim 1, further comprising:

a passivation layer disposed over the source electrode and the drain electrode;

a pixel electrode disposed on the passivation layer, and

wherein the passivation layer has a contact hole, and the pixel electrode is connected with the drain electrode through the contact hole.