Power MOSFET and methods for forming the same
First Claim
1. A device comprising:
- a semiconductor region of a first conductivity type;
a trench extending into the semiconductor region;
a field plate in the trench, wherein the field plate is conductive;
a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region;
a main gate in the trench and overlapping the field plate;
a second dielectric layer between and separating the main gate and the field plate from each other, wherein the second dielectric layer comprises a bottom surface;
a Doped Drain (DD) region of the first conductivity type under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region, and the DD region comprises a to surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer;
a body region comprising a first portion at a same level as a portion of the main gate, and a second portion underlying and contacting the bottom surface of the second dielectric layer, wherein the body region is of a second conductivity type opposite the first conductivity type; and
a Metal-Oxide-Semiconductor (MOS) containing device at a surface of the semiconductor region, wherein the MOS containing device is selected from the group consisting essentially of a High Voltage (HV)N-type MOS (HVNMOS) device, an HV P-type MOS (HVPMOS) device, a Low Voltage (LV)N-type MOS (LVNMOS) device, an LV P-type MOS (LVPMOS) device, and combinations thereof.
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Accused Products
Abstract
A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.
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Citations
21 Claims
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1. A device comprising:
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a semiconductor region of a first conductivity type; a trench extending into the semiconductor region; a field plate in the trench, wherein the field plate is conductive; a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region; a main gate in the trench and overlapping the field plate; a second dielectric layer between and separating the main gate and the field plate from each other, wherein the second dielectric layer comprises a bottom surface; a Doped Drain (DD) region of the first conductivity type under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region, and the DD region comprises a to surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer; a body region comprising a first portion at a same level as a portion of the main gate, and a second portion underlying and contacting the bottom surface of the second dielectric layer, wherein the body region is of a second conductivity type opposite the first conductivity type; and a Metal-Oxide-Semiconductor (MOS) containing device at a surface of the semiconductor region, wherein the MOS containing device is selected from the group consisting essentially of a High Voltage (HV)N-type MOS (HVNMOS) device, an HV P-type MOS (HVPMOS) device, a Low Voltage (LV)N-type MOS (LVNMOS) device, an LV P-type MOS (LVPMOS) device, and combinations thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A device comprising:
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a semiconductor region of a first conductivity type selected from the group consisting essentially of p-type and n-type; a trench power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising; a trench extending from a top surface of the semiconductor region into the semiconductor region; a first dielectric layer lining a bottom and sidewalls of the trench; a field plate comprising a bottom and sidewalls contacting the first dielectric layer, wherein the field plate is conductive; a main gate in the trench and overlapping the field plate; a second dielectric layer between and separating the main gate and the field plate from each other; and a Doped Drain (DD) region of the first conductivity type, wherein the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, wherein the DD region has an impurity concentration greater than an impurity concentration of the semiconductor region, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer; and a lateral MOS device at a surface of the semiconductor region. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A device comprising:
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a semiconductor region of a first conductivity type; a trench extending from a top surface of the semiconductor region into the semiconductor region; a first dielectric layer lining a bottom and sidewalls of the trench; a field plate comprising a bottom and sidewalls contacting the first dielectric layer, wherein the field plate is conductive; a second dielectric layer over and contacting the field plate; a Doped Drain (DD) region of the first conductivity type, wherein the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, wherein the DD region has an impurity concentration greater than an impurity concentration of the semiconductor region; a main gate in the trench, wherein an edge portion of the main gate overlaps the DD region, wherein the second dielectric layer is between and separates the main gate and the field plate from each other, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer; and a lateral MOS device at a surface of the semiconductor region. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification