High threshold voltage NMOS transistors for low power IC technology
First Claim
1. An integrated circuit includinga plurality of transistors of benchmark design of a first conductivity type, each said transistor of said benchmark design including a stressed layer or film applying stress on a channel of said transistor of benchmark design to cause increased electron mobility in said channel, said stressed film also causing out-diffusion of impurities from said channel such that no halo implant is formed therein;
- andat least one transistor of a different design of said first conductivity type exhibiting reduced leakage and increased threshold voltage compared with said plurality of transistors of benchmark design, said at least one transistor of a different design having a channel region with a higher concentration of impurities than channels regions of said plurality of transistors of benchmark design, wherein said higher concentration forms a halo implant in said channel region of said at least one transistor of a different design,wherein a total impurity dose in a channel region of a transistor of said benchmark design and in material adjacent said channel region of said transistor of said benchmark design and a total impurity dose in a channel region of said at least one transistor of said different design are substantially equal but differently distributed such that halo implants are present in said channel region of said at least one transistor of different design but not present in channel regions of said plurality of transistors of said benchmark design, such that a total impurity dose within each channel region of said plurality of transistors of benchmark design is less than said total impurity dose in said channel region of said at least one transistor of said different design and such that a total impurity content of said integrated circuit is substantially equal to the a total impurity content required to form halo implants in all transistors of both said benchmark design and different design.
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Accused Products
Abstract
Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
27 Citations
10 Claims
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1. An integrated circuit including
a plurality of transistors of benchmark design of a first conductivity type, each said transistor of said benchmark design including a stressed layer or film applying stress on a channel of said transistor of benchmark design to cause increased electron mobility in said channel, said stressed film also causing out-diffusion of impurities from said channel such that no halo implant is formed therein; - and
at least one transistor of a different design of said first conductivity type exhibiting reduced leakage and increased threshold voltage compared with said plurality of transistors of benchmark design, said at least one transistor of a different design having a channel region with a higher concentration of impurities than channels regions of said plurality of transistors of benchmark design, wherein said higher concentration forms a halo implant in said channel region of said at least one transistor of a different design, wherein a total impurity dose in a channel region of a transistor of said benchmark design and in material adjacent said channel region of said transistor of said benchmark design and a total impurity dose in a channel region of said at least one transistor of said different design are substantially equal but differently distributed such that halo implants are present in said channel region of said at least one transistor of different design but not present in channel regions of said plurality of transistors of said benchmark design, such that a total impurity dose within each channel region of said plurality of transistors of benchmark design is less than said total impurity dose in said channel region of said at least one transistor of said different design and such that a total impurity content of said integrated circuit is substantially equal to the a total impurity content required to form halo implants in all transistors of both said benchmark design and different design. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification