Semiconductor die terminal

• US 8,970,031 B2
• Filed: 06/15/2010
• Issued: 03/03/2015
• Est. Priority Date: 06/16/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US13/319,145
• Publication Number:
  US 20120049342A1
• Time in Patent Office: 1,722 Days
• Field of Search: 257/734, 257/E23.01, 257/E21.599, 257/E21.508, 257/E23.021, 438/113, 438/613
• US Class Current: 257/734
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11505 Sintering
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/11902 Multiple masking steps
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.

Claims

1. A method of making multilayered semiconductor die terminals, the method comprising the steps of:

printing at least a first mask layer selectively on at least a portion of a wafer containing a plurality of the semiconductor devices;

creating first recesses in the first mask layer aligned with electrical terminals on the semiconductor devices;

plating a conductive material in a plurality of the first recesses to form die terminals for the electrical terminal on the semiconductor devices;

printing a second mask layer selectively on the first mask layer after plating the conductive material in the first recesses;

creating second recesses in the second mask layer aligned with the conductive material in the first recesses;

plating a conductive material in the second recesses that is electrically coupled to the conductive material in the first recesses to extend the die terminals on the semiconductor devices;

removing the first and second mask layers to expose multilayered die terminals; and

dicing the wafer into a plurality of discrete semiconductor devices.

2. The method of claim 1 wherein the second recesses have a cross-sectional area different than a cross-sectional area of the first recesses.

3. The method of claim 1 wherein the conductive material deposited in the first recesses is different from the conductive material deposited in the second recesses.

4. The method of claim 1 comprising the step of plating the multilayered die terminals.

5. The method of claim 1 wherein the step of:

printing a third mask layers selectively on at least a portion of the second mask layer;

creating third recesses in the third mask layer aligned with the second recesses;

plating a conductive material in the third recesses to create multilayered die terminals configured to flex when the semiconductor devices is mechanically coupled with another circuit member.

6. The method of claim 1 comprising:

printing at least one electrical device in at least one of the recesses; and

electrically coupling the electrical device to a multilayered die terminal.

7. The method of claim 6 wherein the electrical device is selected from one of transistors, capacitors, resistors, RF antennae, shielding, filters, signal or power altering and enhancing devices, memory devices, embedded IC, optical fibers, printed optical quality material, coaxial structures, or printed micro strip RF circuits.

8. The method of claim 1 comprising depositing one or more of a non-conductive material or a semi-conductive material in one or more of the recesses.

9. The method of claim 1 comprising the steps of:

locating pre-formed conductive materials in one or more of the recesses; and

plating the recesses to form die terminals with substantially cross-sectional shapes corresponding to a cross-sectional shape of the first recesses.

10. The method of claim 1 comprising the steps of:

pressing conductive foil into at least a portion of the recesses;

shearing the conductive foil along edges of the recesses;

removing excess conductive foil not located in the recesses; and

plating the recesses to form conductive traces with substantially rectangular cross-sectional shapes.

11. A semiconductor with die terminals made according to the method of claim 1.