High power FET switch
First Claim
1. A stacked FET switch comprising:
- a field effect transistor (FET) device stack that is operable in an open state and in a closed state, the FET device stack comprising a plurality of FET devices coupled in series to form the FET device stack, each of the plurality of FET devices having a gate contact, a drain contact, and a source contact;
a control circuit operably associated with the FET device stack, the control circuit being configured to;
bias the gate contact of each of the plurality of FET devices at a first voltage and bias the drain contact and the source contact of each of the plurality of FET devices at a second voltage such that the FET device stack operates in the closed state;
the first voltage being positive relative to a reference voltage;
bias the gate contact of each of the plurality of FET devices at the second voltage and bias the drain contact and the source contact of each of the plurality of FET devices at the first voltage, such that the FET device stack operates in the open state; and
the second voltage being lower than the first voltage and substantially non-negative relative to the reference voltage.
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Accused Products
Abstract
Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. A control circuit provides biasing voltages to the gate, source, and drain contacts of each of the plurality of FET devices to switch the FET device stack to and from a closed state and an open state. In the open state, the gate contacts of each of the plurality of FET devices are biased by the control circuit at the second voltage. To prevent activation in the open state, the control circuit biases the drain contacts and source contacts of each of the plurality of FET devices at the first voltage. The first voltage is positive relative to a reference voltage, such as ground, while the second voltage is non-negative relative to the reference voltage but less than the first voltage.
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Citations
23 Claims
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1. A stacked FET switch comprising:
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a field effect transistor (FET) device stack that is operable in an open state and in a closed state, the FET device stack comprising a plurality of FET devices coupled in series to form the FET device stack, each of the plurality of FET devices having a gate contact, a drain contact, and a source contact; a control circuit operably associated with the FET device stack, the control circuit being configured to; bias the gate contact of each of the plurality of FET devices at a first voltage and bias the drain contact and the source contact of each of the plurality of FET devices at a second voltage such that the FET device stack operates in the closed state; the first voltage being positive relative to a reference voltage; bias the gate contact of each of the plurality of FET devices at the second voltage and bias the drain contact and the source contact of each of the plurality of FET devices at the first voltage, such that the FET device stack operates in the open state; and the second voltage being lower than the first voltage and substantially non-negative relative to the reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 22, 23)
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13. A stacked FET switch comprising:
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a field effect transistor (FET) device stack that is operable in an open state and in a closed state, the FET device stack comprising a plurality of FET devices coupled in series to form the FET device stack, each of the plurality of FET devices having a gate contact, a body contact, a drain contact, and a source contact; a control circuit operably associated with the FET device stack and configured to; positively bias the gate contact of each of the plurality of FET devices and substantially non-negatively bias the drain contact and the source contact of each of the plurality of FET devices relative to a reference voltage such that the FET device stack operates in the closed state; positively bias the drain contact and the source contact of each of the plurality of FET devices relative to the reference voltage and substantially non-negatively bias the gate contact of each of the plurality of FET devices relative to the reference voltage, such that the FET device stack operates in the open state; and a resistive circuit coupled to the body contact of each of the plurality of FET devices, the resistive circuit providing a high resistance at the body contact of each of the plurality of FET devices so as to render one or more parasitic capacitances associated with a transistor body of each of the plurality of FET devices negligible. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A stacked FET switch comprising:
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a field effect transistor (FET) device stack that is operable in an open state and in a closed state, the FET device stack comprising a plurality of FET devices coupled in series to form the FET device stack, each of the plurality of FET devices having a gate contact, a body contact, a drain contact, and a source contact; a control circuit operably associated with the FET device stack, the control circuit being configured to; apply a first bias voltage to the gate contact of each of the plurality of FET devices and apply a second bias voltage to the drain contact and the source contact of each of the plurality of FET devices such that the FET device stack operates in the closed state, wherein the first bias voltage is positive relative to a reference voltage; and apply the first bias voltage to at least one of the drain contact or the source contact of at least one of the plurality of FET devices and apply the second bias voltage to the gate contact of each of the plurality of FET devices, such that the FET device stack operates in the open state, wherein the second bias voltage is substantially non-negative relative to the reference voltage; and a resistive circuit coupled to the body contact of each of the plurality of FET devices, the resistive circuit providing a high resistance at the body contact of each of the plurality of FET devices so as to render one or more parasitic capacitances associated with a transistor body of each of the plurality of FET devices negligible. - View Dependent Claims (21)
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Specification