Circuits and devices for generating bi-directional body bias voltages, and methods therefor

• US 8,970,289 B1
• Filed: 01/22/2013
• Issued: 03/03/2015
• Est. Priority Date: 01/23/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Lee, Sang-Soo, Kuo, Augustine, Rogenmoser, Robert, Boling, Edward J.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US13/747,268
• Time in Patent Office: 770 Days
• Field of Search: None
• US Class Current: 327/534
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

An integrated circuit device can include at least a first bi-directional biasing circuit having a first substrate portion containing a plurality of first transistors; a first control digital-to-analog converter (DAC) to generate any of a plurality of first target values in response to a first target code; a first detect circuit configured to generate a difference value between the first target values and a first limit value; and at least a first charge pump circuit configured to drive the first substrate portion between a forward body bias voltage and a reverse body bias voltage for the first transistors in response to first target values. Embodiments can also include a performance monitor section configured to determine a difference between the voltage of the first substrate portion and a target voltage. Control logic can generate first code values in response to the difference between the voltage of the first substrate portion and the target voltage. Methods are also disclosed.

Claims

1. An integrated circuit device, comprising:

at least a first bi-directional biasing circuit that includes

a first substrate portion containing a plurality of first transistors;

a first control digital-to-analog converter (DAC) to generate any of a plurality of first target values in response to a first target code;

a first detect circuit configured to generate a difference value between the first target values and a first limit value; and

at least a first charge pump circuit configured to drive the first substrate portion between a forward body bias voltage and a reverse body bias voltage for the first transistors in response to the first target values.

2. The integrated circuit device of claim 1, wherein:

the first detect circuit is selected from a transconductance amplifier that generates a current difference value and a voltage amplifier that generates a voltage difference value.

3. The integrated circuit device of claim 1, wherein:

the at least first charge pump circuit includes

a pump controller that generates periodic control values, and

a charge pump that drives the first substrate portion between the forward and reverse body bias voltages in response to the periodic control values.

4. The integrated circuit device of claim 1, further including:

a first reference DAC configured to generate the first limit value from a plurality of limit values in response to limit codes.

5. The integrated circuit device of claim 1, wherein:

the integrated circuit device is coupled to receive a high supply voltage (VDD);

the first substrate portion comprises n-type semiconductor; and

the forward body bias voltage is less than VDD and the reverse body bias voltage is greater than VDD.

6. The integrated circuit device of claim 1, wherein:

the integrated circuit device is coupled to receive a low supply voltage (VSS);

the first substrate portion comprises p-type semiconductor; and

the forward body bias voltage is greater than VSS and the reverse body bias voltage is less than VSS.

7. The integrated circuit device of claim 1, further including:

a second bi-directional biasing circuit that includes

a second substrate portion containing a plurality of second transistors;

a second charge pump circuit coupled to the second substrate portion;

a second control DAC to generate any of a plurality of second target values in response to a second target code;

a second detect circuit configured to generate a difference value between the second target values and a second limit value; and

the second charge pump circuit configured to drive the second substrate portion between a second forward body bias voltage and a second reverse body bias voltage for the second transistors in response to the second target values.

8. The integrated circuit device of claim 1, wherein:

at least some of the transistors have an enhanced body coefficient by way of a doped region having a dopant concentration of greater than 1×

10¹⁸ dopant atoms/cm³.

9. An integrated circuit device, comprising:

at least a first bi-directional biasing circuit configured to drive a first substrate portion containing first transistors to a driven body bias voltage that is between a reverse body bias voltage and a forward body bias voltage in response to first code values;

a performance monitor section coupled to at least the first substrate portion and configured to determine a difference between the driven body bias voltage and a first target voltage; and

control logic coupled to at least the first bi-directional biasing circuit and configured to generate the first code values in response to the difference between the driven body bias voltage and the first target voltage.

10. The integrated circuit device of claim 9, further including:

the integrated circuit device receives a low power supply voltage (VSS);

the first substrate portion is a p-type semiconductor region; and

the reverse body bias voltage is less than VSS and the forward body bias voltage is greater than VSS.

11. The integrated circuit device of claim 10, further including:

the integrated circuit device receives a high power supply voltage (VDD);

a second bi-directional biasing circuit configured to drive an n-type semiconductor region to a second driven body bias voltage between a p-type reverse body bias voltage, greater than VDD, and a p-type forward body bias voltage, less than VDD, in response to second code values;

the performance monitor section is further coupled to the n-type semiconductor region and configured to determine a difference between the second driven body bias voltage and a second target voltage; and

the control logic is further coupled to the second bi-directional biasing circuit and configured to generate the second code values in response to the difference between the second driven body bias voltage and the second target voltage.

12. The integrated circuit device of claim 9, wherein:

at least some of said first transistors have an enhanced body coefficient from a doped body below a substantially undoped channel region, the doped body having a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³.

13. The integrated circuit device of claim 9, wherein:

the performance monitor section includes

an oscillator circuit configured to generate a performance oscillating signal having a frequency that varies according to the driven body bias voltage; and

a detector configured to generate a detect signal corresponding to a difference between the performance oscillating signal and a target oscillating signal corresponding to the first target voltage.

14. The integrated circuit device of claim 13, wherein:

the control logic includes

a counter circuit configured to generate a count value from the difference between the performance and target oscillating signals; and

DAC control logic configured to generate at least the first code values in response to the count value from the counter circuit.

15. The integrated circuit device of claim 9, further including:

a plurality of sections, each including second transistors formed in different second substrate portions;

a different bi-directional biasing circuit coupled to each second substrate portion, and configured to drive its second substrate portion between second reverse and second forward body bias voltages in response to received second code values; and

the control logic also generates the second code values for the different bi-directional biasing circuit.

16. The integrated circuit device of claim 15, wherein:

the sections are selected from the group of;

digital circuits, analog circuits, input/output circuits, and sections with transistors having different structures from one another.

17. An integrated circuit device, comprising:

a bi-directional body bias generator configured to generate forward and reverse body bias voltages for a plurality of transistors, including

a first digital-to-analog converter (DAC) configured to determine a first current flowing through a first load to generate a first voltage,

a second DAC configured to determine a second current flowing through a second load to generate a second voltage,

an amplifier configured to generate a detect value in response to the first and second voltages,

an oscillator coupled to receive the detect value and generate a plurality of clock signals, and

at least one charge pump configured to generate either the forward or reverse body bias voltage in response to at least one of the clock signals.

18. The integrated circuit device of claim 17, wherein:

the amplifier is selected from the group consisting of;

a transconductance amplifier and a voltage amplifier.

19. The integrated circuit device of claim 17, wherein:

the oscillator is selected from the group consisting of;

a current controlled oscillator and a voltage controlled oscillator.

20. The integrated circuit device of claim 17, wherein:

the first load is coupled between an output node and the first DAC; and

the at least one charge pump generates the forward or reverse body bias voltage at the output node.