Amplifiers and related biasing methods and devices
First Claim
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1. A biasing method comprising:
- providing an amplifier having an amplifier output node, the amplifier comprising a plurality of amplifier MOSFET devices;
sensing an output voltage at the amplifier output node through a plurality of sensing MOSFET devices arranged in a cascode configuration, a gate terminal of one of the plurality of sensing MOSFET devices being connected with the amplifier output node; and
generating one or more bias voltages proportional to the output voltage to bias gate terminals of the plurality of amplifier MOSFET devices.
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Abstract
Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.
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Citations
9 Claims
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1. A biasing method comprising:
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providing an amplifier having an amplifier output node, the amplifier comprising a plurality of amplifier MOSFET devices; sensing an output voltage at the amplifier output node through a plurality of sensing MOSFET devices arranged in a cascode configuration, a gate terminal of one of the plurality of sensing MOSFET devices being connected with the amplifier output node; and generating one or more bias voltages proportional to the output voltage to bias gate terminals of the plurality of amplifier MOSFET devices. - View Dependent Claims (2, 3)
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4. A biasing method comprising:
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providing an amplifier having an amplifier output node, the amplifier comprising a plurality of amplifier MOSFET devices; providing two biasing circuits each comprising a first stack and a second stack, wherein each of the first stack and second stack comprises a plurality of MOSFET devices arranged in a cascode configuration and a plurality of resistors arranged in series with the plurality of MOSFET devices; and sensing an output voltage at the amplifier output at a gate terminal of one of the plurality of MOSFET devices of the first stack and at a gate terminal of one of the plurality of MOSFET devices of the second stack; and generating, for each biasing circuit, one or more bias voltages proportional to the output voltage to bias gate terminals of the plurality of amplifier MOSFET devices. - View Dependent Claims (5, 6, 7, 8)
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9. A biasing method comprising:
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providing an amplifier differential input stage comprising; an input common mode voltage node of two input transistors paired differentially; a current source comprising cascoded transistors for generating bias current of the input stage; and a plurality of amplifier devices in series with the two input transistors; and providing a biasing circuit comprising; a first stack comprising; a plurality of biasing MOSFET devices of a first type arranged in cascode configuration; and a plurality of series resistors arranged in series with the plurality of biasing MOSFET devices of the first type; and a second stack comprising; a plurality of biasing MOSFET devices of a second type, opposite to the first type, arranged in a cascode configuration; and a plurality of series resistors arranged in-series with the plurality of biasing MOSFET devices of the second type; wherein; a gate terminal of the one of the plurality of biasing MOSFET devices of the first type and a gate terminal of one of the plurality of biasing MOSFET devices of the second type are connected with an input common mode node of the amplifier differential input stage and, during operation, currents proportional to an input common mode voltage generated at the input common mode node flow through the series resistors within the biasing circuit to produce bias voltages to gate terminals of the plurality of the amplifier MOSFET devices, wherein the second stack generates bias voltages for the amplifier devices when the input common mode voltage increases; and the first stack generates bias voltages for the current source when the input common mode voltage decreases.
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Specification