Amplifiers and related biasing methods and devices

• US 8,970,303 B2
• Filed: 01/07/2013
• Issued: 03/03/2015
• Est. Priority Date: 09/01/2010
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Lam, Fleming
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/735,830
• Publication Number:
  US 20140022016A1
• Time in Patent Office: 785 Days
• Field of Search: 330/253, 330/255, 330/258, 330/261, 330/285, 330/296
• US Class Current: 330/261
• CPC Class Codes: H03F 1/0272 by using a signal derived from the output signal
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/471 the voltage being sensed
• CPC Class Codes: H03F 2203/30063 A differential amplifier being used in the bias circuit or in the control circuit of the SEPP-amplifier
• CPC Class Codes: H03F 2203/45024 the differential amplifier amplifying transistors are cascode coupled transistors
• CPC Class Codes: H03F 2203/45244 the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
• CPC Class Codes: H03F 2203/45311 the common gate stage of a cascode dif amp being implemented by multiple transistors
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier

Abstract

Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.

Claims

1. A biasing method comprising:

providing an amplifier having an amplifier output node, the amplifier comprising a plurality of amplifier MOSFET devices;

sensing an output voltage at the amplifier output node through a plurality of sensing MOSFET devices arranged in a cascode configuration, a gate terminal of one of the plurality of sensing MOSFET devices being connected with the amplifier output node; and

generating one or more bias voltages proportional to the output voltage to bias gate terminals of the plurality of amplifier MOSFET devices.

2. The biasing method of claim 1, wherein the one or more bias voltages are generated by an in-series arrangement of resistors.

3. The biasing method of claim 1, wherein the plurality of amplifier MOSFET devices are arranged in a cascode configuration.

4. A biasing method comprising:

providing an amplifier having an amplifier output node, the amplifier comprising a plurality of amplifier MOSFET devices;

providing two biasing circuits each comprising a first stack and a second stack, wherein each of the first stack and second stack comprises a plurality of MOSFET devices arranged in a cascode configuration and a plurality of resistors arranged in series with the plurality of MOSFET devices; and

sensing an output voltage at the amplifier output at a gate terminal of one of the plurality of MOSFET devices of the first stack and at a gate terminal of one of the plurality of MOSFET devices of the second stack; and

generating, for each biasing circuit, one or more bias voltages proportional to the output voltage to bias gate terminals of the plurality of amplifier MOSFET devices.

5. The biasing method of claim 4, wherein the plurality of MOSFET devices of the first stack are PMOS devices while the plurality of MOSFET devices of the second stack are NMOS devices.

6. The biasing method of claim 4, wherein

during a first state the plurality of MOSFET devices of the second stack is biased at a first gate voltage, while the plurality of MOSFET devices of the first stack is biased at a second gate voltage lower than the first gate voltage;

and

during a second state the plurality of MOSFET devices of the first stack is biased at a third gate voltage, while the plurality of MOSFET devices of the second stack is biased at a fourth gate voltage lower than the third gate voltage.

7. The biasing method of claim 6, wherein the first state and second state are dependent on the output voltage from the amplifier output node such that the first state occurs upon increase of the output voltage and the second state occurs upon decrease of the output voltage.

8. The biasing method of claim 6, wherein

during the first state, the generating one or more bias voltages is done across the plurality of resistors in series with the plurality of MOSFET devices of the second stack at a first bias current level, while the generating one or more bias voltages is done across the plurality of resistors in series with the plurality of MOSFET devices of the first stack at a second bias current level lower than the first bias current level;

during the second state, the generating one or more bias voltages is done across the plurality of resistors in series with the plurality of MOSFET devices of the first stack at a third bias current level, while the generating one or more bias voltages is done across the plurality of resistors in series with the plurality of MOSFET devices of the second stack at a fourth bias current level lower than the third bias current level, the method further comprising

providing the one or more biasing voltages generated by the plurality of resistors to respective gate terminals of the plurality of amplifier MOSFET devices.

9. A biasing method comprising:

providing an amplifier differential input stage comprising;

an input common mode voltage node of two input transistors paired differentially;

a current source comprising cascoded transistors for generating bias current of the input stage; and

a plurality of amplifier devices in series with the two input transistors; and

providing a biasing circuit comprising;

a first stack comprising;

a plurality of biasing MOSFET devices of a first type arranged in cascode configuration; and

a plurality of series resistors arranged in series with the plurality of biasing MOSFET devices of the first type; and

a second stack comprising;

a plurality of biasing MOSFET devices of a second type, opposite to the first type, arranged in a cascode configuration; and

a plurality of series resistors arranged in-series with the plurality of biasing MOSFET devices of the second type;

wherein;

a gate terminal of the one of the plurality of biasing MOSFET devices of the first type and a gate terminal of one of the plurality of biasing MOSFET devices of the second type are connected with an input common mode node of the amplifier differential input stage and, during operation,

currents proportional to an input common mode voltage generated at the input common mode node flow through the series resistors within the biasing circuit to produce bias voltages to gate terminals of the plurality of the amplifier MOSFET devices, wherein

the second stack generates bias voltages for the amplifier devices when the input common mode voltage increases; and

the first stack generates bias voltages for the current source when the input common mode voltage decreases.