Level shifter, system-on-chip including the same, and multimedia device including the same
First Claim
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1. A level shifter, comprising:
- an input node;
a voltage shifter connected between the input node and configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node; and
an output node connected to the shifter and configured to output the output clock,wherein the voltage shifter includes a first voltage shifter circuit and a second voltage shifter circuit having a same structure and connected in parallel between the input node and the output node, wherein the first voltage shifter circuit includes at least two inverters operating at the second voltage domain, the at least two inverters directly connected in series between the input node and the output node, and wherein the second voltage shifter circuit includes at least one first inverter operating at the first voltage domain and at least one second inverter operating at the second voltage domain, wherein the at least one first inverter and the at least one second inverter are directly connected in series between the input node and the output node.
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Abstract
Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.
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Citations
20 Claims
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1. A level shifter, comprising:
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an input node; a voltage shifter connected between the input node and configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node; and an output node connected to the shifter and configured to output the output clock, wherein the voltage shifter includes a first voltage shifter circuit and a second voltage shifter circuit having a same structure and connected in parallel between the input node and the output node, wherein the first voltage shifter circuit includes at least two inverters operating at the second voltage domain, the at least two inverters directly connected in series between the input node and the output node, and wherein the second voltage shifter circuit includes at least one first inverter operating at the first voltage domain and at least one second inverter operating at the second voltage domain, wherein the at least one first inverter and the at least one second inverter are directly connected in series between the input node and the output node. - View Dependent Claims (2)
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3. A level shifter, comprising:
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an input node; a voltage shifter connected between the input node and configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node; and an output node connected to the shifter and configured to output the output clock, wherein the voltage shifter includes a first voltage shifter circuit and a second voltage shifter circuit having a same structure and connected in parallel between the input node and the output node, wherein; the first voltage shifter circuit includes a first inverter configured to output a second voltage or a ground voltage according to a voltage of the input node, and a second inverter configured to output the second voltage or the ground voltage to the output node according to an output of the first inverter, and the second voltage shifter circuit includes a third inverter configured to output the first voltage or the ground voltage according to a voltage of the input node, and a fourth inverter configured to output the second voltage or the ground voltage to the output node according to an output of the third inverter. - View Dependent Claims (4)
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5. A system-on-chip, comprising:
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a phase locked loop configured to generate a first clock of a first voltage domain; a peripheral block, an audio block, a display block, a graphic block, an image processing block, and a codec block operating in response to the first clock; a level shifter configured to generate a second clock of a second voltage domain based upon the first clock; and a processor operating in response to the second clock, wherein the level shifter includes first and second voltage shifter circuits that are configured to have a same structure and are connected in parallel between an input node and an output node, wherein the first voltage shifter circuit includes at least two inverters which operates at the second voltage domain and are directly connected in series between the input node and the output node, wherein the second voltage shifter circuit includes at least one first inverter operating at the first voltage domain and at least one second inverter operating at the second voltage domain, wherein the at least one first inverter and the at least one second inverter are directly connected in series between the input node and the output node. - View Dependent Claims (6, 7)
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8. A multimedia device, comprising:
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a processor; a working memory of the processor; a modem configured to communicate with an exterior according to a control of the processor; a storage unit configured to store data according to a control of the processor; an user interface configured to sense an external signal and to transfer the sensed signal to the processor; a display control unit configured to display an image via a display unit according to a control of the processor; a sound control unit configured to output a sound via a speaker according to a control of the processor; a codec unit configured to perform encoding and decoding operations according to a control of the processor; a clock generating unit configured to generate a clock according to an output of an oscillator; a phase locked loop configured to generate a first clock of a first voltage domain synchronized with the clock; and a level shifter configured to generate a second clock of a second voltage domain in response to the first clock, wherein the processor operates in response to the second clock, and wherein the level shifter includes; a first inverter operating at the second voltage domain and having a first input connected to the input node; a second inverter operating at the second voltage domain, having a second input connected to a first output of the first inverter, and having a second output connected to the output node; a third inverter operating at the first voltage domain and having a third input connected to the input node; and a fourth inverter operating at the second voltage domain, having a fourth input connected to a third output of the third inverter, and having a fourth output connected to the output node. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A level shifter, comprising:
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a first inverter operating at a second voltage domain and having a first input connected to an input node; a second inverter operating at the second voltage domain, having a second input connected to a first output of the first inverter, and having a second output connected to an output node; a third inverter operating at the first voltage domain and having a third input connected to the input node; and a fourth inverter operating at the second voltage domain, having a fourth input connected to a third output of the third inverter, and having a fourth output connected to the output node, wherein an input signal belong to the first voltage domain is input to the input node, and wherein an output signal belong to the second voltage domain is output from the output node.
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Specification