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Pseudo-8T NVSRAM cell with a charge-follower

  • US 8,971,113 B2
  • Filed: 10/28/2013
  • Issued: 03/03/2015
  • Est. Priority Date: 10/30/2012
  • Status: Active Grant
First Claim
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1. A 10T NVSRAM memory cell circuit with a pair of flash-based transistors as a charger, the 10T NVSRAM memory cell comprising:

  • a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two inverters, each inverter including a PMOS device connected to a first power line and a NMOS device connected to a second power line, the first power line and the second power line being operated between a VDD power supply and ground and being separated from a common Nwell node; and

    a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second Flash transistor and a first/second Charger transistor connected in series, the first Flash transistor having a first drain node coupled to the first data node, the second Flash transistor having a second drain node coupled to the second data node, the first Charger transistor having a first source node left floating, the second Charger transistor having a second source node left floating, the first Flash transistor and the second Flash transistor being commonly gated by a second word line, the first Charger transistor and the second Charger transistor being commonly gated by a pump word line;

    wherein the first Charger transistor and the second Charger transistor are configured to ramp the pump word line up to a high voltage above the VDD level to generate charges and respectively pass through the first Flash transistor with a first threshold level and the second Flash transistor with a second threshold level to create a voltage level difference at the first data node and the second data node by subsequently ramping the second word line to the VDD level, the two cross-coupled inverters are operated to amplify the voltage level difference to a scale of VSS=0V at one of the first data node and the second data node and the VDD level at another one of the first data node and the second data node.

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