Pseudo-8T NVSRAM cell with a charge-follower

• US 8,971,113 B2
• Filed: 10/28/2013
• Issued: 03/03/2015
• Est. Priority Date: 10/30/2012
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US14/064,220
• Publication Number:
  US 20140119119A1
• Time in Patent Office: 491 Days
• Field of Search: 365/185.08, 365/185.24
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

The present invention discloses a 10T NVSRAM cell with a 6T SRAM cell with 4T Flash cell with one dedicated Flash-based Charger. In addition, a Pseudo-8T NVSRAM cell with a shared Flash-based Charger between two adjacent 8T NVSRAM cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%. As opposed to the prior art of 12T NVSRAM cell, the Store operation of the above two preferred embodiments use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower ensured by the Flash-based Charger to obtain the final ΔV_Q-QB>0.2V at Q and QB nodes of each SRAM cell to cover all the mismatched of parasitic capacitance in flash cell devices and layout for a reliable amplification by ramping up SRAM'"'"'s VDD line and ramping down SRAM'"'"'s VSS line.

Claims

1. A 10T NVSRAM memory cell circuit with a pair of flash-based transistors as a charger, the 10T NVSRAM memory cell comprising:

a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two inverters, each inverter including a PMOS device connected to a first power line and a NMOS device connected to a second power line, the first power line and the second power line being operated between a VDD power supply and ground and being separated from a common Nwell node; and

a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second Flash transistor and a first/second Charger transistor connected in series, the first Flash transistor having a first drain node coupled to the first data node, the second Flash transistor having a second drain node coupled to the second data node, the first Charger transistor having a first source node left floating, the second Charger transistor having a second source node left floating, the first Flash transistor and the second Flash transistor being commonly gated by a second word line, the first Charger transistor and the second Charger transistor being commonly gated by a pump word line;

wherein the first Charger transistor and the second Charger transistor are configured to ramp the pump word line up to a high voltage above the VDD level to generate charges and respectively pass through the first Flash transistor with a first threshold level and the second Flash transistor with a second threshold level to create a voltage level difference at the first data node and the second data node by subsequently ramping the second word line to the VDD level, the two cross-coupled inverters are operated to amplify the voltage level difference to a scale of VSS=0V at one of the first data node and the second data node and the VDD level at another one of the first data node and the second data node.

2. The 10T NVSRAM memory cell of claim 1 wherein each of the first Flash transistor and the second Flash transistor is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

3. The 10T NVSRAM memory cell of claim 1 wherein each of the first Charger transistor and the second Charger transistor is a same type as each of the first Flash transistor and the second Flash transistor no matter that is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

4. The 10T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Read and Write operation by setting the first word line to the VDD level if the SRAM cell is selected or to VSS=0V if the SRAM cell is not selected and applying the VDD level to the first power line, VSS to the second power line and the pump word line, while setting the second word line to VSS=0V if the threshold levels of the first Flash transistor and the second Flash transistor are all positive or setting the second word line to a lowest negative threshold level if the threshold levels of the first Flash transistor and the second Flash transistor are all negative, to isolated each SRAM cell from each corresponding Flash cell.

5. The 10T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to an Erase operation including a preset step by setting both the first data node and the second data node to VSS under a condition of setting the first word line to the VDD level, the first power line to VSS, the second power line to VSS, the first bit line and the second bit line to VSS, followed by an erase step by applying a positive high voltage VPP to the second word line to increase threshold levels of both the first Flash transistor and the second Flash transistor to a level above the VDD level under a FN-channel scheme in less than 5 ms, along with a Don'"'"'t care state for the pump word line.

6. The 10T NVSRAM memory cell of claim 4 wherein the positive voltage VPP is about +18V for a 2-poly floating-gate type flash transistor or about +10V for a 1-poly charge-trapping type flash transistor, and the VDD level is about 1V to 2V.

7. The 10T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

1”

of the SRAM cell with the first data node at the VDD level and the second data node at VSS=0V, the Program operation further including a programming step of ramping the second word line from VSS to a negative high voltage VNN using a FN-edge scheme to decrease the first threshold level of the first Flash transistor to a first final level and to decrease the second threshold level of the second Flash transistor to a second final level along with a Don'"'"'t care state for the pump word line, the first final level being lower than the second final level by at least 1V, thereby storing the flash logic state “

0”

in the Flash cell.

8. The 10T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

0”

of the SRAM cell with the first data node at VSS=0V and the second data node at the VDD level, the Program operation including a programming step of ramping the second word line from VSS to a negative high voltage VNN using a FN-edge scheme to decrease the first threshold level of the first Flash transistor to a first final level and to decrease the second threshold level of the second Flash transistor to a second final level along with a Don'"'"'t care state for the pump word line, the first final level being higher than the second final level by at least 1V, thereby storing the flash logic state “

1”

in the Flash cell.

9. The 10T NVSRAM memory cell of claim 8 wherein the negative voltage VNN is ranging from −

15V to −

18V for a 2-poly floating-gate type flash transistor or about −

10V for a 1-poly charge-trapping type flash transistor.

10. The 10T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a Store operation comprises using a FN-channel erase operation followed by a FN-edge program operation to write a loaded logic state from the SRAM cell to the Flash cell.

11. The 10T NVSRAM memory cell of claim 10 wherein the FN-channel erase operation comprises using +15V or greater positive voltage at the second word line along with VSS at the pump word line to increase threshold levels of the first Flash transistor and the second Flash transistor to a same level substantially above the VDD level.

12. The 10T NVSRAM memory cell of claim 11 wherein the FN-edge program operation comprises using −

15V or greater negative voltage at the second word line along with VSS at the pump word line to decrease threshold level of one of the first Flash transistor and the second Flash transistor to a level below the VDD level while keep another threshold level of another one of the first Flash transistor and the second Flash transistor to a level remained above the VDD level.

13. The 10T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Recall operation for writing a flash logic state stored in the Flash cell back to the first data node and the second data node under a charge-sensing scheme assisted by the first Charger transistor and the second Charger transistor, the flash logic state including at least a state “

1”

defined by assigning the first threshold level at Vt1 for the first Flash transistor and the second threshold level at Vt0<

Vt1 for the second Flash transistor or a state “

0”

defined by assigning the first threshold level at Vt0 for the first Flash transistor and the second threshold level at Vt1>

Vt0 for the second Flash transistor.

14. The 10T NVSRAM memory cell of claim 13 wherein the Vt0 is preferred to be a negative value about −

2V and the Vt1 is preferred to be a positive value above the VDD level.

15. The 10T NVSRAM memory cell of claim 13 wherein the Recall operation for writing the flash logic state “

0”

to the SRAM cell comprises initializing the SRAM cell with the first data node and the second data node, the first bit line and the second bit line, the first power line and the second power line all at VSS=0V by pulsing the first word line to the VDD level, and setting the second word line and the pump word line to VSS, followed by firstly ramping the second power line from VSS to the VDD level, secondly ramping the pump word line from VSS to a level substantially above the VDD level, and thirdly ramping the second word line from VSS to the VDD level, and sequentially ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step followed by ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step.

16. The 10T NVSRAM memory cell of claim 15 wherein firstly ramping the second power line from VSS to the VDD level comprises forming a reversed bias condition for the two Inverters of the SRAM cell to prevent charges in the first data node and the second data node from leaking.

17. The 10T NVSRAM memory cell of claim 15 wherein secondly ramping the pump word line from VSS to the level substantially above the VDD level comprises keeping voltage level of the pump word line below a programming voltage VPP of +18V for generating coupling charges in drain nodes of the first Charger transistor and the second Charger transistor, the coupling charges being coupled through the first Flash transistor to the first data node with a first level of charges and coupled through the second Flash transistor to the second data node with a second level of charges, the first level being higher than the second level due to Vt0<

Vt1.

18. The 10T NVSRAM memory cell of claim 17 wherein thirdly ramping the second word line from VSS to the VDD level comprises using a charge voltage-follower operation through the first Flash transistor to push the first level of charges at the first data node to a third level of charges and through the second Flash transistor to push the second level of charges at the second data node to a fourth level of charges, the third level being higher than the fourth level due to Vt0<

Vt1.

19. The 10T NVSRAM memory cell of claim 18 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step comprises pulling up the third level of charges at the first data node to substantially the VDD level and pulling up the fourth level of charges at the second data node to a fifth level of charges, the fifth level being lower than the VDD level.

20. The 10T NVSRAM memory cell of claim 19 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step comprises pulling down the fifth level of charges at the second data node to VSS=0V while maintaining the VDD level at the first data node.

21. The 10T NVSRAM memory cell of claim 19 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step comprises coupling the second word line to a negative bias voltage below a lowest threshold level to turn off both the first Flash transistor and the second Flash transistor.

22. The 10T NVSRAM memory cell of claim 20 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step comprises coupling the second word line to a negative bias voltage below a lowest threshold level to turn off both the first Flash transistor and the second Flash transistor.

23. The 10T NVSRAM memory cell of claim 15 wherein the Recall operation further comprises setting the first word line to the VDD level and resetting the first power line to the VDD level, the second power line to VSS, and the second word line to VSS to return to a SRAM operation with a loaded SRAM logic state “

1”

associated with the VDD level at the first data node and VSS at the second data node.

24. A paired pseudo-8T NVSRAM memory cell circuit with a shared flash charger, the paired pseudo-8T NVSRAM memory cell comprising:

a first pseudo-8T NVSRAM cell having a first flash source terminal and second flash source terminal;

a second pseudo-8T NVSRAM cell having a third flash source terminal and fourth flash source terminal; and

a first Charger transistor and a second Charger transistor commonly gated by a pump word line, the first Charger transistor having a first charger drain node connected to the first flash source terminal and a first charger source node connected to the third flash source terminal, the second Charger transistor having a second charger drain node connected to the second flash source terminal and a second charger source node connected to the fourth flash source terminal;

wherein the first pseudo-8T NVSRAM cell and the second pseudo-8T NVSRAM cell are configured to be substantially same in a NVSRAM cell structure sharing separately a first common power line and a second common power line respectively operated between a VDD power supply and ground, the NVSRAM cell structure comprising,

a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two inverters, each inverter including a PMOS device connected to the first power line and a NMOS device connected to the second power line, the first power line and the second power line being separated from a common Nwell node; and

a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second Flash transistor, the first Flash transistor having a first drain node and a first source node, the first drain node being coupled to the first data node, the second Flash transistor having a second drain node and a second source node, the second drain node being coupled to the second data node, the first Flash transistor and the second Flash transistor being commonly gated by a second word line;

wherein the first/second source node of the first pseudo-8T NVSRAM cell is the first/second flash source terminal and the first/second source node of the second pseudo-8T NVSRAM cell is the third/fourth flash source terminal;

wherein the first Charger transistor and the second Charger transistor are configured to ramp the pump word line up to a high voltage above the VDD level to generate charges and use a charge-sensing scheme and voltage-follower operation for performing a Recall operation to write a Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in either the first pseudo-8T NVSRAM cell or the second pseudo-8T NVSRAM cell to corresponding SRAM logic state stored by voltage levels of the first data node and the second data node in corresponding the first pseudo-8T NVSRAM cell or the second pseudo-8T NVSRAM cell.

25. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein each of the first Flash transistor and the second Flash transistor in either the first pseudo-8T NVSRAM cell or the second pseudo-8T NVSRAM cell is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

26. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein each of the first Charger transistor and the second Charger transistor is a same type as each of the first Flash transistor and the second Flash transistor no matter that is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

27. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein the SRAM cell in either the first pseudo-8T NVSRAM cell or the second pseudo-8T NVSRAM cell is subjected to a Read and Write operation by setting the first word line to the VDD level if the SRAM cell is selected or to VSS=0V if the SRAM cell is not selected and applying the VDD level to the first power line, VSS to the second power line and the pump word line, while setting the second word line to VSS=0V if the threshold levels of the first Flash transistor and the second Flash transistor are all positive or at least below a lowest negative threshold level if one threshold level of the first Flash transistor and the second Flash transistor is a negative value, to isolated each SRAM cell from each corresponding Flash cell.

28. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein the Flash cell in either the first pseudo-8T NVSRAM cell or the second pseudo-8T NVSRAM cell is subjected to an Erase operation including a preset step by setting both the first data node and the second data node to VSS under a condition of setting the first word line to the VDD level, the first power line to VSS, the second power line to VSS, the first bit line and the second bit line to VSS, followed by an erase step by applying a positive high voltage VPP to the second word line to increase threshold levels of both the first Flash transistor and the second Flash transistor to a level above the VDD level under a FN-channel scheme in less than 5 ms, along with a Don'"'"'t care state for the pump word line.

29. The paired pseudo-8T NVSRAM memory cell of claim 28 wherein the positive voltage VPP is about +18V for a 2-poly floating-gate type flash transistor or about +10V for a 1-poly charge-trapping type flash transistor, and the VDD level is about 1V to 2V.

30. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein the Flash cell in either the first pseudo-8T NVSRAM cell or the second pseudo-8T NVSRAM cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

1”

of the SRAM cell with the first data node at the VDD level and the second data node at VSS=0V, the Program operation including a programming step of ramping the second word line from VSS to a negative high voltage VNN using a FN-edge scheme to decrease threshold level of the first Flash transistor to a first final level and to decrease threshold level of the second Flash transistor to a second final level along with a Don'"'"'t care state for the pump word line, the first final level being lower than the second final level by at least 1V, thereby storing the flash logic state “

0”

in the Flash cell.

31. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein the Flash cell in either the first pseudo-8T NVSRAM cell or the second pseudo-8T NVSRAM cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

0”

of the SRAM cell with the first data node at VSS=0V and the second data node at the VDD level, the Program operation including a programming step of ramping the second word line from VSS to a negative high voltage VNN using a FN-edge scheme to decrease threshold level of the first Flash transistor to a first final level and to decrease threshold level of the second Flash transistor to a second final level along with a Don'"'"'t care state for the pump word line, the first final level being higher than the second final level by at least 1V, thereby storing the flash logic state “

1”

in the Flash cell.

32. The paired pseudo-8T NVSRAM memory cell of claim 31 wherein the negative voltage VNN is ranging from −

15V to −

18V for a 2-poly floating-gate type flash transistor or about −

10V for a 1-poly charge-trapping type flash transistor.

33. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein each SRAM cell in both the first pseudo-8T NVSRAM cell and the second pseudo-8T NVSRAM cell is simultaneously subjected to a Recall operation for writing a flash logic state stored in corresponding Flash cell back to the first data node and the second data node under a charge-sensing scheme assisted by the first Charger transistor and the second Charger transistor, the flash logic state including at least a state “

1”

defined by assigning the first threshold level at Vt1 for the first Flash transistor and the second threshold level at Vt0<

Vt1 for the second Flash transistor or a state “

0”

defined by assigning the first threshold level at Vt0 for the first Flash transistor and the second threshold level at Vt1>

Vt0 for the second Flash transistor.

34. The paired pseudo-8T NVSRAM memory cell of claim 33 wherein the Recall operation for writing the flash logic state “

0”

to the SRAM cell comprises initializing the SRAM cell with the first data node and the second data node, the first bit line and the second bit line, the first power line and the second power line all at VSS=0V by pulsing the first word line to the VDD level, and setting the second word line and pump word line to VSS, followed by firstly ramping the second power line from VSS to the VDD level, secondly ramping the pump word line from VSS to a level substantially above the VDD level, and thirdly ramping the second word line from VSS to the VDD level, followed by sequentially ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level and ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level.

35. The paired pseudo-8T NVSRAM memory cell of claim 34 wherein ramping the second power line from VSS to the VDD level comprises forming a reversed bias condition for the two Inverters of the SRAM cell to prevent charges in the first data node and the second data node from leaking.

36. The paired pseudo-8T NVSRAM memory cell of claim 34 wherein ramping the pump word line from VSS to the level substantially above the VDD level comprises keeping voltage level of the pump word line below a programming voltage VPP of +18V for generating coupling charges in drain nodes of the first Charger transistor and the second Charger transistor, the coupling charges being coupled through the first Flash transistor to the first data node with a first level of charges and coupled through the second Flash transistor to the second data node with a second level of charges, the first level being higher than the second level due to Vt0<

Vt1.

37. The paired pseudo-8T NVSRAM memory cell of claim 36 wherein ramping the second word line from VSS to the VDD level comprises using a charge voltage-follower operation through the first Flash transistor to push the first level of charges at the first data node to a third level of charges and through the second Flash transistor to push the second level of charges at the second data node to a fourth level of charges, the third level being higher than the fourth level due to Vt0<

Vt1.

38. The paired pseudo-8T NVSRAM memory cell of claim 37 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level comprises pulling up the third level of charges at the first data node to substantially the VDD level in a first SRAM amplification operation and pulling up the fourth level of charges at the second data node to a fifth level of charges, the fifth level being lower than the VDD level.

39. The paired pseudo-8T NVSRAM memory cell of claim 38 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level comprises pulling down the fifth level of charges at the second data node to VSS=0V in a second SRAM amplification operation while maintaining the VDD level at the first data node.

40. The paired pseudo-8T NVSRAM memory cell of claim 38 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level comprises coupling the second word line to a negative bias voltage to turn off both the first Flash transistor and the second Flash transistor to ensure the first SRAM amplification operation in the first pseudo-8T NVSRAM cell free from any cross-talk with the first SRAM amplification in the second pseudo-8T NVSRAM cell.

41. The paired pseudo-8T NVSRAM memory cell of claim 39 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level comprises coupling the second word line to a negative bias voltage to turn off both the first Flash transistor and the second Flash transistor to ensure the second SRAM amplification operation in the first pseudo-8T NVSRAM cell free from any cross-talk with the second SRAM amplification in the second pseudo-8T NVSRAM cell.

42. The paired pseudo-8T NVSRAM memory cell of claim 34 wherein the Recall operation further comprises setting the first word line to the VDD level and resetting the first power line to the VDD level, the second power line to VSS, and the second word line to VSS if the Vt0 is a positive value or to at least below a lowest negative threshold level if the Vt0 is a negative value to return to a SRAM operation with a loaded SRAM logic state “

1”

associated with the VDD level at the first data node and VSS at the second data node in the corresponding SRAM cell.

43. The paired pseudo-8T NVSRAM memory cell of claim 33 wherein the Vt0 is preferred to be a negative value about −

2V and the Vt1 is preferred to be a positive value above the VDD level.

44. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein the first Charger transistor and the second Charger transistor are configured to optionally have their channel lengths doubled for generating doubled charges shared with the first pseudo-8T NVSRAM cell and the second pseudo-8T NVSRAM cell enough for performing the Recall operation under the charge-sensing scheme when the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the first pseudo-8T NVSRAM cell is same as the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the second pseudo-8T NVSRAM cell.

45. The paired pseudo-8T NVSRAM memory cell of claim 24 wherein the first Charger transistor and the second Charger transistor are configured to have their original channel lengths for generating the charges separately for the first pseudo-8T NVSRAM cell and the second pseudo-8T NVSRAM cell enough for performing the Recall operation under the charge-sensing scheme when the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the first pseudo-8T NVSRAM cell is opposite to the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the second pseudo-8T NVSRAM cell.