Method and devices for memory cell erasure with a programming monitor of reference cells

• US 8,971,121 B2
• Filed: 08/20/2013
• Issued: 03/03/2015
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Mihnea, Andrei
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US13/971,075
• Publication Number:
  US 20130343127A1
• Time in Patent Office: 560 Days
• Field of Search: 365/185.29, 365/185.33, 365/185.11, 365/185.19, 365/185.2, 365/185.22, 365/185.17
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

Claims

1. A method for operating an array of memory cells, the method comprising:

erasing a selected group of memory cells that includes a number of reference cells and a number of data cells;

performing a programming monitor operation on the number of erased reference cells; and

determining a number of operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of erased reference cells.

2. The method of claim 1, further comprising performing the programming monitor operation on the number of erased reference cells prior to performing a programming operation on the number of data cells.

3. The method of claim 1, including performing the programming monitor operation as part of an erase operation.

4. The method of claim 1, wherein the method includes determining an amount of the number of reference cells having a threshold voltage above a particular voltage level in response to the programming monitor operation.

5. The method of claim 1, wherein the selected group of memory cells comprises a block of memory cells, and wherein the method includes storing data corresponding to the determined number of particular operating parameters within the block of memory cells.

6. The method of claim 1, wherein performing the programming monitor operation on the number of erased reference cells includes applying a programming voltage pulse having a particular magnitude to the number of reference cells, and wherein the particular magnitude is greater than an initial programming pulse voltage magnitude associated with programming the number of data cells.

7. A memory device comprising:

an array of memory cells including data cells and reference cells; and

control circuitry coupled to the array and configured to;

erase a selected group of memory cells including a number of data cells and a number of reference cells;

perform a programming monitor operation on the number of reference cells prior to performing a programming operation on at least one of the number of data cells; and

at least partially based on the programming monitor operation, adjust a number of operating parameters associated with operating the number of data cells.

8. The memory device of claim 7, wherein the number of operating parameters comprise a number of operating voltages.

9. The memory device of claim 8, wherein the number of operating voltages comprise at least one of a programming start voltage, a program step voltage, and an erase verify voltage.

10. The memory device of claim 7, wherein the control circuitry is configured to perform the programming monitor operation as part of an erase operation.

11. The memory device of claim 7, wherein the control circuitry is configured to determine a program performance of the number of reference cells based on the programming monitor operation.

12. The memory device of claim 11, wherein the control circuitry is configured to determine the program performance of the number of reference cells by applying a particular read voltage to the number of reference cells and determining an amount of the number of reference cells that conduct current in response to the application of the particular read voltage.

13. A memory device, comprising:

an array of memory cells including data cells and reference cells; and

control circuitry coupled to the array and configured to;

apply a programming signal to a number of erased reference cells;

determine an amount of the number of erased reference cells whose threshold voltage reaches a particular level in response to the applied programming signal;

select an adjusted set of operating parameters based, at least partially, on the determined amount of the number of erased reference cells whose threshold voltage reaches the particular level in response to the applied programming signal; and

program a number of data cells using at least one adjusted programming parameter from the adjusted set of particular operating parameters.

14. The memory device of claim 13, wherein the programming signal is a programming voltage signal applied to an access line to which the number of erased reference cells are coupled.

15. The memory device of claim 13, wherein the control circuitry is configured to apply the programming signal to the number of erased memory cells as part of an erase operation.

16. The memory device of claim 13, wherein the number of erased reference cells and the number of data cells are coupled to a same access line.

17. The memory device of claim 13, wherein the at least one adjusted programming parameter includes an adjusted programming start voltage.

18. The memory device of claim 13, wherein the control circuitry is configured to apply the programming signal to a number of erased reference cells as part of a programming monitor operation.

19. The memory device of claim 13, wherein the array is a NAND array comprising a number of blocks of memory cells.

20. The memory device of claim 19, wherein at least one of the number of blocks includes only one NAND string of reference cells.