Semiconductor memory device capable of shortening erase time

• US 8,971,130 B2
• Filed: 10/25/2012
• Issued: 03/03/2015
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shibata, Noboru
• Primary Examiner(s): DINH, SON T
• Application Number:
  US13/660,044
• Publication Number:
  US 20130051155A1
• Time in Patent Office: 859 Days
• Field of Search: 365/185.29, 365/185.18, 365/185.19, 365/185.22
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Claims

1. A semiconductor memory device comprising:

a memory cell array in which memory cells are arranged in a matrix;

word lines, including a first word line, a second word line and third word lines, connected to the memory cells, and the third word lines located between the first and second word lines; and

a control circuit,

wherein the memory cell array has blocks, each of the blocks has a NAND string which includes at least two select transistors and memory cells connected in series between the select transistors, the select transistors have gates connected to at least two select lines, the first word line is connected to at least one of the memory cells next to at least one of the select transistors in the NAND string, and the second word line is connected to at least another one of the memory cells next to at least another one of the select transistors in the NAND string, and

wherein the control circuit erases one of the blocks in an erase operation, and the control circuit, in the erase operation, sets a first voltage to the first word line, sets a second voltage to the second word line, and sets a third voltage less than the first and second voltages to the third word lines.

2. The device according to claim 1, further comprising

first transistors connected to the select lines;

a second transistor connected to the first word line;

a third transistor connected to the second word line; and

fourth transistors connected to the third word lines,

wherein gates of the first, second, third and fourth transistors are connected in common.

3. The device according to claim 2,

wherein in the erase operation, gates of the first, second, third and fourth transistors are set to a fourth voltage greater than a fifth voltage supplied to the select lines, and a sixth voltage greater than or equal to the fifth voltage is supplied to the first word and second lines.

4. The device according to claim 2,

wherein in the erase operation, gates of the first, second, third and fourth transistors are set to a seventh voltage greater than an eighth voltage supplied to the select lines minus a voltage Vth, wherein Vth is a threshold voltage of the first, second, third and fourth transistors, and the eighth voltage is supplied to the first and second word lines.

5. The device according to claim 2,

wherein the control circuit, in the erase operation, sets a ninth voltage greater than the first and second voltages to the select lines.

6. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells and a plurality of dummy memory cells;

a plurality of word lines and dummy word lines connected to the plurality of memory cells and a plurality of dummy memory cells; and

a control circuit,

wherein the plurality of memory cells are arranged in a matrix, the memory cell array has a plurality of blocks, each of the blocks has a plurality of NAND strings, each of the NAND strings includes two select transistors and series connected memory cells and the dummy memory cells located between the select transistors, the dummy memory cells are disposed next to the select transistors, and a plurality of select lines are connected to the select transistors,

the word lines are connected to the memory cells for storing data,

the dummy word lines are connected to the dummy memory cells, and

wherein the control circuit erases one of the blocks in an erase operation, and the control circuit, in the erase operation, sets a first voltage to the select lines, sets a second voltage less than the first voltage to the dummy word lines, and sets a third voltage less than the second voltage to the word lines.

7. The device according to claim 6, further comprising

first transistors connected to the select lines;

second transistors connected to the dummy word lines; and

third transistors connected to the word lines,

wherein gates of the first, second, and third transistors are connected in common.

8. The device according to claim 7,

wherein in the erase operation, gates of the first, second, and third transistors are set to a fourth voltage greater than the first voltage, and a fifth voltage greater than or equal to the first voltage is supplied to the dummy word lines.

9. The device according to claim 7,

wherein in the erase operation, gates of the first, second, and third transistors are set to a sixth voltage greater than the first voltage minus a voltage Vth, wherein Vth is a threshold voltage of the first, second, and third transistors, and the first voltage is supplied to the dummy word lines.

10. The device according to claim 7,

wherein in the erase operation, gates of the first, second, and third transistors are set to a sixth voltage greater than the first voltage minus a voltage Vth, wherein Vth is a threshold voltage of the first, second, and third transistors), and seventh voltage (less than the first voltage is supplied to the dummy word lines.