Compact high speed sense amplifier for non-volatile memory and hybrid lockout

• US 8,971,141 B2
• Filed: 01/17/2013
• Issued: 03/03/2015
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Mui, Man Lung, Kato, Yosuke, Nguyen, Hao Thai, Lee, Seungpil
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US13/744,219
• Publication Number:
  US 20140003157A1
• Time in Patent Office: 775 Days
• Field of Search: 365/205, 365/203, 365/204, 365/207
• US Class Current: 365/205
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and a second supply level for a data latch of the sense amp. The latch'"'"'s supply level is of a high level that used for driving the bit lines and can be provided by a charge pump. The sense amp need use only NMOS devices for its analog path. For balancing performance and current consumption, the sense amp also includes an additional latch to support a “hybrid lockout” sensing mode, where in a verify operation a read-lockout is used between different data states, but not between the low and high quick pass write (QPW) verifies.

Claims

1. A sense amplifier for a memory circuit, comprising:

an intermediate circuit, including a first node selectively connectable to one or more bit lines;

bit line selection circuitry connected to the first node, whereby the first node is selectively connectable to one or more bit lines;

a pre-charge switch by which the first node is connectable to a first supply level for pre-charging of the first node for a sensing operation;

a first latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node;

a second latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; and

first and second switches whereby the values latched in the first and second latch circuits are respectively transferrable to a data bus,

wherein, in a sensing operation, after pre-charging the first node and prior to a subsequent pre-charging, the first and second data latch circuits are sequentially connectable to have the value latched therein set according to the level of the first node.

2. The sense amplifier of claim 1, wherein the first latch circuit is connected between a second supply level and ground, and the second latch circuit is connected between the first supply level and ground, the second supply level being different than the first supply level.

3. The sense amplifier of claim 2, wherein the second supply level of a higher level that the first supply level.

4. The sense amplifier of claim 3, wherein the memory circuit on which the sense amplifier is formed further includes a charge pump circuit, where the second supply level is provided from the charge pump circuit.

5. The sense amplifier of claim 1, wherein a node of the first latch that holds the value latched therein is connectable to the first node through a third switch.

6. The sense amplifier of claim 5, wherein a node of the first latch that holds the inverted version of the value latched therein is connectable to the first node through a fourth switch.

7. The sense amplifier of claim 1, wherein second latch circuit is used as part of a quick pass write verify.

8. A sense amplifier for a memory circuit, comprising:

an intermediate circuit, including a first node selectively connectable to one or more bit lines;

a first latch circuit selectively connectable to the first node;

bit line selection circuitry connected to the first node, whereby the first node is selectively connectable to one or more bit lines;

a first switch whereby the first latch circuit is connectable to a data bus;

a second switch whereby the first node is selectively connectable to a first voltage supply level; and

a third switch whereby the first node is selectively connectable to an external node, wherein the path between the external node and the first node is formed of only n-type devices, and

wherein when a value held in the first latch circuit is at a high value the first node is cut off from the first voltage supply level, and when the value held in the first latch circuit is at a low value the first node is cut off from the external node.

9. The sense amplifier of claim 8, wherein the first latch circuit is connected between a second supply level and ground, wherein the second supply level of a higher level that the first supply level.

10. The sense amplifier of claim 9, wherein the memory circuit on which the sense amplifier is formed further includes a charge pump circuit, where the second supply level is provided from the charge pump circuit.

11. The sense amplifier of claim 8, wherein the first voltage supply level is used for pre-charging for sensing.

12. The sense amplifier of claim 8, wherein the voltage levels on the external node have a high level less than the first voltage supply level.

13. The sense amplifier of claim 12, wherein the voltage levels on the external node include a bit line value for verify lockout and a bit line value to enable programming.

14. A sense amplifier for a memory circuit comprising:

an intermediate circuit, including a first node selectively connectable to one or more bit lines;

a first latch circuit selectively connectable to the first node;

bit line selection circuitry connected to the first node, whereby the first node is selectively connectable to one or more bit lines;

a first switch whereby the first latch circuit is connectable to a data bus;

a second switch whereby the first node is selectively connectable to a first voltage supply level; and

a third switch whereby the first node is selectively connectable to an external node, wherein the path between the external node and the first node is formed of only n-type devices, wherein when a value held in the first latch circuit is at a high value the first node is cut off from the first voltage supply level, and when the value held in the first latch circuit is at a low value the first node is cut off from the external node;

a pre-charge switch by which the first node is connectable to the first voltage supply level for pre-charging of the first node for a sensing operation;

a second latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; and

a fourth switch whereby the value latched in the second latch circuit is transferrable to the data bus,

wherein, in a sensing operation, after pre-charging the first node and prior to a subsequent pre-charging, the first and second data latch circuits is selectively connectable to have the value latched therein set according to the level of the first node.

15. The sense amplifier of claim 14, wherein a node of the first latch that holds the value latched therein is connectable to the first node through a sixth switch.

16. The sense amplifier of claim 15, wherein a node of the first latch that holds the inverted version of the value latched therein is connectable to the first node through a seventh switch.

17. The sense amplifier of claim 14, wherein second latch circuit is used as part of a quick pass write verify.

18. The sense amplifier of claim 17, wherein the voltage levels on the external node include a bit line value to inhibit programming and a hit line value to partially inhibit programming.