Systems and methods for locking an oscillator to an incoming data signal

• US 8,971,423 B1
• Filed: 03/10/2010
• Issued: 03/03/2015
• Est. Priority Date: 03/10/2010
• Status: Active Grant

• Current Assignee: Smsc Holdings Sarl
• Original Assignee: Smsc Holdings Sarl
• Inventors: Fu, Wei, An, Hongming, Ye, Jun, Nie, Bin
• Primary Examiner(s): Fan, Chieh M
• Assistant Examiner(s): Hassan, Sarah
• Application Number:
  US12/721,432
• Time in Patent Office: 1,819 Days
• Field of Search: 375/260, 375/376, 327/20
• US Class Current: 375/260
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H04K 1/10 by using two signals transmitted simultaneously or successively

Abstract

In one example, a system includes an oscillator adapted to provide an oscillator signal, a frequency divider adapted to divide the oscillator signal to provide a divided oscillator signal, and a phase-frequency detector adapted to provide phase-frequency detection signals in response to a reference clock signal and the divided oscillator signal. The system also includes a charge pump adapted to provide first output signals in response to the phase-frequency detection signals, a phase detector adapted provide second output signals in response to an incoming data signal and the oscillator signal, and one or more switches adapted to pass the first output signals during a frequency acquisition mode and pass the second output signals during a phase lock mode. The system also includes an active filter adapted to filter the passed first or second output signals. The oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or second output signals.

Claims

1. A system comprising:

an oscillator adapted to provide an oscillator signal;

a frequency divider adapted to divide the oscillator signal to provide a divided oscillator signal;

a phase-frequency detector adapted to provide phase-frequency detection signals in response to a reference clock signal and to the divided oscillator signal;

a charge pump adapted to provide first output signals in response to the phase-frequency detection signals;

a phase detector adapted to provide phase detection signals in response to an incoming data signal and to the oscillator signal;

adjustable resistors adapted to provide second output signals in response to the phase detection signals;

one or more switches adapted to pass the first output signals during a frequency acquisition mode and pass the second output signals during a phase lock mode wherein no charge pump is used in providing the second output signals during the phase lock mode; and

an active filter adapted to filter the passed first or the passed second output signals, wherein the oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or the filtered second output signals.

2. The system of claim 1, wherein:

the phase-frequency detector, the charge pump, the one or more switches, the active filter, the oscillator, and the frequency divider provide a frequency acquisition loop adapted to adjust a frequency of the divided oscillator signal during the frequency acquisition mode to substantially lock the divided oscillator signal with a frequency of the reference clock signal;

the phase detector, the one or more switches, the active filter, and the oscillator provide a phase locking loop adapted to adjust a phase of the oscillator signal during the phase lock mode to substantially lock the oscillator signal with a phase of the incoming data signal; and

the oscillator signal corresponds to a recovered clock associated with the incoming data signal after the oscillator signal is substantially locked with the phase of the incoming data signal.

3. The system of claim 1, wherein the incoming data signal is a high speed data signal and the reference clock signal is a low speed clock signal.

4. The system of claim 3, wherein the incoming data signal is an approximately GHz clock signal and the reference clock signal is an approximately 20 MHz clock signal.

5. The system of claim 3, wherein the incoming data signal is a Universal Serial Bus (USB) 3.0 Super Speed signal.

6. The system of claim 1, wherein the charge pump comprises a common-mode feedback loop adapted to stabilize a common-mode voltage of the charge pump during the frequency acquisition mode to improve a dynamic range of the first output signals.

7. The system of claim 1, wherein the active filter comprises a common-mode feedback loop adapted to stabilize a common-mode voltage of the active filter during the phase lock mode to improve a dynamic range of the second output signals.

8. The system of claim 7, wherein the system is adapted to set the common-mode voltage of the active filter to approximately a common-mode voltage of the second output signals to reduce disturbance when the system switches from the frequency acquisition mode to the phase lock mode.

9. The system of claim 1, further comprising a passive filter interposed between the active filter and the oscillator, wherein the passive filter comprises one or more adjustable resistors and one or more adjustable capacitors.

10. A method comprising:

providing an oscillator signal using an oscillator;

dividing the oscillator signal using a frequency divider to provide a divided oscillator signal;

providing phase-frequency detection signals from a phase-frequency detector in response to a reference clock signal and to the divided oscillator signal;

providing first output signals from a charge pump in response to the phase-frequency detection signals;

providing phase detection signals from a phase detector in response to an incoming data signal and to the oscillator signal;

providing second output signals from one or more adjustable resistors in response to the phase detection signals;

switching between passing the first output signals during a frequency acquisition mode and passing the second output signals during a phase lock mode wherein no charge pump is used in providing the second output signals the during phase lock mode; and

filtering the passed first or the passed second output signals using an active filter, wherein the oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or the filtered second output signals.

11. The method of claim 10, further comprising:

adjusting a frequency of the divided oscillator signal to substantially lock the divided oscillator signal with a frequency of the reference clock signal during the frequency acquisition mode;

adjusting a phase of the oscillator signal to substantially lock, the oscillator signal with a phase of the incoming data signal; and

wherein the oscillator signal corresponds to a recovered clock associated with the incoming data signal after the oscillator signal is substantially locked with the phase of the incoming data signal.

12. The method of claim 10, wherein the incoming data signal is a high speed data signal and the reference clock signal is a low speed clock signal.

13. The method of claim 12, wherein the incoming data signal is an approximately 5 GHz clock signal and the reference clock signal is an approximately 20 MHz clock signal.

14. The method of claim 12, wherein the incoming data signal is a Universal Serial Bus (USB) 3.0 Super Speed signal.

15. The method of claim 10, stabilizing a common-mode voltage of the charge pump during the frequency acquisition mode using a common-mode feedback loop of the charge pump to improve a dynamic range of the first output signals.

16. The method of claim 10, stabilizing a common-mode voltage of the active filter during the phase lock mode using a common-mode feedback loop of the active filter to improve a dynamic mime of the second output signals.

17. The method of claim 16, further comprising setting the common-mode voltage of the active filter to approximately a common-mode voltage of the second output signals to reduce disturbance during the switching.

18. The method of claim 10, wherein the filtering further comprises filtering the filtered first or second output signals using a passive filter before the filtered signals are provided to the oscillator.

19. A system comprising:

means for providing an oscillator signal;

means for dividing the oscillator signal to provide a divided oscillator signal;

means for providing phase-frequency detection signals in response to a reference clock signal and to the divided oscillator signal;

means for providing first output signals from a charge pump in response to the phase-frequency detection signals;

means for providing phase detection signals in response to an incoming data signal and to the oscillator signal;

means for providing second output signals from one or more adjustable resistors in response to the phase detection signals;

means for switching between passing the first output signals during a frequency acquisition mode and passing the second output signals during a phase lock mode wherein no charge pump is used in providing the second output signals during the phase lock mode;

means for filtering the passed first or the passed second output signals; and

means for adjusting a frequency of the oscillator signal in response to the filtered first or the filtered second output signals.