Power management of memory circuits by virtual memory simulation
First Claim
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1. An apparatus comprising:
- a plurality of physical memory circuits; and
an interface circuit configured to;
communicate between the plurality of physical memory circuits and a memory controller;
simulate one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits;
receive, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and
issue one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits.
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Abstract
An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
881 Citations
14 Claims
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1. An apparatus comprising:
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a plurality of physical memory circuits; and an interface circuit configured to; communicate between the plurality of physical memory circuits and a memory controller; simulate one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits; receive, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and issue one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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communicating, by an interface circuit, between a plurality of physical memory circuits and a memory controller; simulating, by the interface circuit, one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits; receiving, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and issuing, by the interface circuit, one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits. - View Dependent Claims (8, 9, 10)
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11. An apparatus comprising:
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a memory controller; and a memory module comprising; a plurality of physical memory circuits; and an interface circuit configured to; communicate between the plurality of physical memory circuits and the memory controller; simulate one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits; receive, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and issue one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits. - View Dependent Claims (12, 13, 14)
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Specification