Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin

• US 8,972,707 B2
• Filed: 11/17/2011
• Issued: 03/03/2015
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Stephan
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US13/299,239
• Publication Number:
  US 20120166764A1
• Time in Patent Office: 1,202 Days
• US Class Current: 713/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1423 by reconfiguration of paths
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire.

Claims

1. A dynamically reconfigurable multi-core microprocessor comprising:

a plurality of initially enabled processing cores;

each initially enabled core being configured to execute a kill instruction issued by system software by disabling the core from responding to transactions on a system bus externally coupled to the multi-core microprocessor, thereby disabling the core;

wherein a kill-instruction-disabled core is disabled from complying with a reset message instruction sent over the system bus, but remains operable to be revived by an external reset on a reset pin of the multi-core microprocessor, and, if so reset, to resume operability as an enabled processing core unless and until it receives another kill instruction.

2. The dynamically reconfigurable multi-core microprocessor of claim 1, wherein as a result of being unresponsive to system bus transactions, a core disabled by the kill instruction does not respond to snoop cycles on the system bus.

3. The dynamically reconfigurable multi-core microprocessor of claim 1, wherein each initially enabled core is further configured, in response to the kill instruction, to put itself into a power-conserving sleep state.

4. The dynamically reconfigurable multi-core microprocessor of claim 1, wherein other initially enabled cores not disabled by a kill instruction are configured, by internal power-state management microcode, to coordinate power state management between themselves without accounting for any requested power state value of any disabled cores.

5. A method for dynamically reconfiguring a multi-core microprocessor having a plurality of processing cores, the method comprising:

initially enabling the processing cores;

by each initially enabled core, executing a kill instruction issued by system software by disabling the core from responding to transactions on a system bus externally coupled to the multi-core microprocessor; and

wherein a kill-instruction-disabled core is disabled from complying with a reset message instruction sent over the system bus, but remains operable to be revived by an external reset on a reset pin of the multi-core microprocessor, and, if so reset, to resume operability as an enabled processing core unless and until it receives another kill instruction.

6. The method of claim 5, wherein as a result of being unresponsive to system bus transactions, a core disabled by the kill instruction does not respond to snoop cycles on the system bus.

7. The method of claim 5, further comprising:

by each initially enabled core, in response to the kill instruction, putting itself into a power-conserving sleep state.

8. The method of claim 5, further comprising:

by internal power-state management microcode of other initially enabled cores not disabled by a kill instruction, coordinating power state management between themselves without accounting for any requested power state value of any disabled cores.

9. A computer program product encoded in at least one non-transitory computer usable storage medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a dynamically reconfigurable multi-core microprocessor, the computer usable program code comprising;

program code for specifying a plurality of initially enabled processing cores;

each initially enabled core being configured to execute a kill instruction issued by system software by disabling the core from responding to transactions on a system bus externally coupled to the multi-core microprocessor, thereby disabling the core; and

wherein a kill-instruction-disabled core is disabled from complying with a reset message instruction sent over the system bus, but remains operable to be revived by an external reset on a reset pin of the multi-core microprocessor, and, if so reset, to resume operability as an enabled processing core unless and until it receives another kill instruction.

10. The computer program product of claim 9, wherein as a result of being unresponsive to system bus transactions, a core disabled by the kill instruction does not respond to snoop cycles on the system bus.

11. The computer program product of claim 9, wherein each initially enabled core is further configured, in response to the kill instruction, to put itself into a power-conserving sleep state.

12. The computer program product of claim 9, wherein other initially enabled cores not disabled by a kill instruction are configured, by internal power-state management microcode, to coordinate power state management between themselves without accounting for any requested power state value of any disabled cores.