Computing core application access utilizing dispersed storage

• US 8,972,774 B2
• Filed: 12/30/2013
• Issued: 03/03/2015
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Cleversafe Incorporated (International Business Machines Corporation)
• Inventors: Grube, Gary W., Markison, Timothy W.
• Primary Examiner(s): PATEL, KAMINI B
• Application Number:
  US14/143,524
• Publication Number:
  US 20140115388A1
• Time in Patent Office: 428 Days
• Field of Search: 714/6.1
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to fetch an instruction from the processing module and determines whether the instruction is currently stored in the main memory. When the instruction is not currently stored in the main memory, the memory controller determines whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices; and, when it is, the memory controller addresses the DSN memory to retrieve the one or more sets of encoded instruction slices. When at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, the one or more sets of encoded instruction slices are decoded using a dispersed storage error coding function to reconstruct the instruction, which is provided to the processing module.

Claims

1. A set of circuits for a computing device comprises:

a processing module; and

a memory controller operably coupled to the processing module, wherein the memory controller is operable to;

utilize a memory map of memory of the computing device, wherein the memory map identifies a user section and a kernel section within the memory, wherein the user section includes a plurality of pillars and the kernel section includes a plurality of pillars;

facilitate reading of data by the processing module from the memory by;

determining whether the data is stored as one or more sets of encoded data slices;

when the data is stored as the one or more sets of encoded data slices;

determining whether the data is user data or system data;

when the data is user data, retrieving, for each of the one or more sets of encoded data slices, an encoded user data slice from a threshold number of pillars of the plurality of pillars in the user section;

decoding the retrieved encoded user data slices in accordance with a dispersed storage error coding function to produce the user data; and

sending the user data to the processing module.

2. The set of circuits of claim 1, wherein the memory controller is further operable to:

when the data is system data, retrieve, for each of the one or more sets of encoded data slices, an encoded system data slice from a threshold number of pillars of the plurality of pillars in the kernel section;

decode the retrieved encoded system data slices in accordance with a dispersed storage error coding function to produce the system data; and

send the system data to the processing module.

3. The set of circuits of claim 1, wherein the memory controller is further operable to:

when the data is not stored as one or more sets of encoded data slices;

determine whether the data is the user data or the system data;

when the data is the user data, retrieve the user data from the user section; and

when the data is the system data, retrieve the system data from the kernel section.

4. The set of circuits of claim 1, wherein the data comprises at least a portion of one or more of:

an application;

a software driver; and

an operating system.

5. The set of circuits of claim 1, wherein the memory controller is further operable to:

facilitate writing the data by the processing module to the memory by;

determining whether the data is to be stored as the one or more sets of encoded data slices;

when the data is to be stored as the one or more sets of encoded data slices;

determining whether the data is the user data or the system data;

when the data is the user data;

encoding the user data in accordance with the dispersed storage error coding function to produce one or more sets of encoded user data slices; and

sending the one or more sets of encoded user data slices to the memory, wherein, for each of the one or more sets of encoded user data slices, the encoded user data slices are stored in different pillars of the plurality of pillars of the user section.

6. The set of circuits of claim 5, wherein the memory controller is further operable to:

when the data is the system data;

encoding the system data in accordance with the dispersed storage error coding function to produce one or more sets of encoded system data slices; and

sending the one or more sets of encoded system data slices to the memory, wherein, for each of the one or more sets of encoded system data slices, the encoded system data slices are stored in different pillars of the plurality of pillars of the kernel section.

7. The set of circuits of claim 1, wherein the memory comprises:

a plurality of random access memory (RAM) devices of main memory of the computing device.

8. The set of circuits of claim 1, wherein the memory comprises:

a plurality of read only memory (ROM) devices of a basic input output system (BIOS) memory of the computing device.

9. The set of circuits of claim 1, wherein the memory comprises:

a plurality of non-core memory devices of the computing device.

10. A computer readable storage device comprises:

a first section that stores operational instructions that, when executed by a computing device, causes the computing device to utilize a memory map of memory of the computing device, wherein the memory map identifies a user section and a kernel section within the memory, wherein the user section includes a plurality of pillars and the kernel section includes a plurality of pillars; and

a second section that stores operational instructions that, when executed by a computing device, causes the computing device to;

facilitate reading of data from the memory by;

determining whether the data is stored as one or more sets of encoded data slices;

when the data is stored as the one or more sets of encoded data slices;

determining whether the data is user data or system data;

when the data is user data, retrieving, for each of the one or more sets of encoded data slices, an encoded user data slice from a threshold number of pillars of the plurality of pillars in the user section;

decoding the retrieved encoded user data slices in accordance with a dispersed storage error coding function to produce the user data; and

sending the user data to the processing module.

11. The computer readable storage device of claim 10, wherein the second section further stores operational instructions that, when executed by a computing device, causes the computing device to:

when the data is system data, retrieve, for each of the one or more sets of encoded data slices, an encoded system data slice from a threshold number of pillars of the plurality of pillars in the kernel section;

decode the retrieved encoded system data slices in accordance with a dispersed storage error coding function to produce the system data; and

send the system data to the processing module.

12. The computer readable storage device of claim 10, wherein the second section further stores operational instructions that, when executed by a computing device, causes the computing device to:

when the data is not stored as one or more sets of encoded data slices;

determine whether the data is the user data or the system data;

when the data is the user data, retrieve the user data from the user section; and

when the data is the system data, retrieve the system data from the kernel section.

13. The computer readable storage device of claim 10, wherein the data comprises at least a portion of one or more of:

an application;

a software driver; and

an operating system.

14. The computer readable storage device of claim 10, wherein the second section further stores operational instructions that, when executed by a computing device, causes the computing device to:

facilitate writing the data to the memory by;

determining whether the data is to be stored as the one or more sets of encoded data slices;

when the data is to be stored as the one or more sets of encoded data slices;

determining whether the data is the user data or the system data;

when the data is the user data;

encoding the user data in accordance with the dispersed storage error coding function to produce one or more sets of encoded user data slices; and

sending the one or more sets of encoded user data slices to the memory, wherein, for each of the one or more sets of encoded user data slices, the encoded user data slices are stored in different pillars of the plurality of pillars of the user section.

15. The computer readable storage device of claim 10, wherein the second section further stores operational instructions that, when executed by a computing device, causes the computing device to:

when the data is the system data;

encode the system data in accordance with the dispersed storage error coding function to produce one or more sets of encoded system data slices; and

send the one or more sets of encoded system data slices to the memory, wherein, for each of the one or more sets of encoded system data slices, the encoded system data slices are stored in different pillars of the plurality of pillars of the kernel section.

16. The computer readable storage device of claim 10, wherein the memory comprises:

a plurality of random access memory (RAM) devices of main memory of the computing device.

17. The computer readable storage device of claim 10, wherein the memory comprises:

a plurality of read only memory (ROM) devices of a basic input output system (BIOS) memory of the computing device.

18. The computer readable storage device of claim 10, wherein the memory comprises:

a plurality of non-core memory devices of the computing device.