Systems and methods for transparently varying error correction code strength in a flash drive

• US 8,972,824 B1
• Filed: 05/22/2012
• Issued: 03/03/2015
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Northcott, Philip L., Geiger, Peter Dau, Sadowsky, Jonathan
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US13/477,599
• Time in Patent Office: 1,015 Days
• Field of Search: 714/773, 714/764, 714/763, 714/758, 714/752, 714/746
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Claims

1. A method of reading data from an array of flash memory devices, the method comprising:

receiving a request for data stored in the flash array, the requested data being identified by a virtual address;

looking up the following, which are associated with the virtual address;

a physical address or addresses of one or more page stripes;

a starting location for the data within the first page stripe of the one or more page stripes of the flash array; and

one or more gear settings for the one or more page stripes, wherein the gear settings are indicative of a strength of error correction assigned to a page stripe of the one or more page stripes;

requesting one or more portions of the payload of the one or more page stripes associated with the virtual address, and providing the one or more gear settings of the one or more page stripes along with the request;

receiving, from an ECC decoder, corrected retrieved portions of the one or more page stripes, and an indication of whether each portion was successfully corrected; and

if all portions of the requested data were successfully corrected by the ECC decoder, reassembling the corrected portions into the requested data and returning the same;

wherein the method is performed by an integrated circuit.

2. The method of claim 1, further comprising:

receiving an indication from the ECC decoder as to whether or not correction for the corrected retrieved data from the flash array has met criteria indicating that a different gear should be selected for the one or more page stripes; and

storing the indication so that when the one or more page stripes are erased and made available for writing, a different gear and corresponding different payload size is used;

wherein the indication is reset after the gear setting has been changed.

3. The method of claim 1, wherein the one or more portions of the payload comprises a first portion from a first page stripe and a second portion from a second page stripe.

4. An apparatus comprising:

a first circuit configured to receive a request for data stored in a flash array, the requested data being identified by a virtual address;

a second circuit configured to look up the following, which are associated with the virtual address;

a physical address or addresses of one or more page stripes;

a starting location for the data within the first page stripe of the one or more page stripes of the flash array; and

one or more gear settings for the one or more page stripes, wherein the gear settings are indicative of a strength of error correction assigned to a page stripe of the one or more page stripes;

the second circuit further configured to request one or more portions of the payload of the one or more page stripes associated with the virtual address, and providing the one or more gear settings of the one or more page stripes along with the request;

the second circuit further configured to receive, from an ECC decoder, corrected retrieved portions of the one or more page stripes, and an indication of whether each portion was successfully corrected; and

if all portions of the requested data were successfully corrected by the ECC decoder, the second circuit is further configured to reassemble the corrected portions into the requested data and return the same.

5. The apparatus of claim 4, wherein the second circuit is further configured to:

receive an indication from the ECC decoder as to whether or not correction for the corrected retrieved data from the flash array has met criteria indicating that a different gear should be selected for the one or more page stripes; and

store the indication so that when the one or more page stripes are erased and made available for writing, a different gear and corresponding different payload size is used;

wherein the second circuit is further configured to reset the indication after the gear setting has been changed.

6. The apparatus of claim 4, wherein the one or more portions of the payload comprises a first portion from a first page stripe and a second portion from a second page stripe.

7. An apparatus for reading data from an array of flash memory devices, the apparatus comprising:

a means for receiving a request for data stored in a flash array, the requested data being identified by a virtual address;

a means for looking up the following, which are associated with the virtual address;

a physical address or addresses of one or more page stripes;

a starting location for the data within the first page stripe of the one or more page stripes of the flash array; and

one or more gear settings for the one or more page stripes, wherein the gear settings are indicative of a strength of error correction assigned to a page stripe of the one or more page stripes;

a means for requesting one or more portions of the payload of the one or more page stripes associated with the virtual address;

a means for providing the one or more gear settings of the one or more page stripes along with the request;

a means for receiving, from an ECC decoder, corrected retrieved portions of the one or more page stripes, and an indication of whether each portion was successfully corrected; and

a means for reassembling;

wherein if all portions of the requested data were successfully corrected by the ECC decoder, the reassembling means further reassembling the corrected portions into the requested data and returning the same.

8. The apparatus of claim 7, further comprising:

a means for receiving an indication from the ECC decoder as to whether or not correction for the corrected retrieved data from the flash array has met criteria indicating that a different gear should be selected for the one or more page stripes;

a means for storing the indication so that when the one or more page stripes are erased and made available for writing, a different gear and corresponding different payload size is used; and

a means for resetting the indication after the gear setting has been changed.

9. The apparatus of claim 7, wherein the one or more portions of the payload comprises a first portion from a first page stripe and a second portion from a second page stripe.