Symmetric placement of components on a chip to reduce crosstalk induced by chip modes

• US 8,972,921 B2
• Filed: 03/14/2013
• Issued: 03/03/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Abraham, David W., Chow, Jerry M., Gambetta, Jay M.
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US13/827,706
• Publication Number:
  US 20140266406A1
• Time in Patent Office: 719 Days
• Field of Search: 716/115
• US Class Current: 716/115
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena

Abstract

A method and system to control crosstalk among qubits on a chip are described. The method includes placing two or more components symmetrically on the chip, the chip including the qubits, and driving two or more ports symmetrically to control the crosstalk based on controlling coupling of chip mode frequencies and qubit frequencies.

Claims

1. A method to control crosstalk among qubits on a chip, the method comprising:

placing two or more components symmetrically on the chip, the two or more components including the qubits and two or more ports;

driving the two or more ports symmetrically, using corresponding two or more drive signals, to control the crosstalk based on controlling coupling of chip mode frequencies and qubit frequencies, the driving symmetrically including each of the two or more drive signals including a same bias as and either a same phase as or a phase 180 degrees different than a phase of one or more other ones of the two or more drive signals.

2. The method according to claim 1, wherein the placing the two or more components includes placing two identical circuits on the chip as mirror images of each other.

3. The method according to claim 2, wherein the driving the two or more ports includes simultaneously driving a same port on each of the two circuits with a drive signal having a same bias and a same phase at each of the two circuits.

4. The method according to claim 1, wherein the placing the two or more components includes placing four identical circuits on the chip.

5. The method according to claim 4, wherein the driving the two or more ports includes simultaneously driving a same port on each of the four circuits, same first drive signals driving each of a first set of diagonal ports and same second drive signals driving each of a second set of diagonal ports.

6. The method according to claim 5, wherein the driving the first set of diagonal ports and the second set of diagonal ports includes the first drive signals and the second drive signals having a same bias and different phase.

7. The method according to claim 1, further comprising identifying a location on the chip corresponding with a node of a chip mode frequency.

8. The method according to claim 7, wherein the placing the two or more components includes placing two ports symmetrically on the chip along the node.

9. The method according to claim 8, wherein the driving includes simultaneously driving the two ports with drive signals, the drive signals having a same bias and a different phase.

10. A system to control crosstalk among qubits on a chip, the system comprising:

two or more components placed symmetrically on the chip, the two or more components including the qubits and two or more ports; and

two or more drive signals applied symmetrically to the two or more ports to control the crosstalk based on controlling coupling of chip mode frequencies and qubit frequencies, the two or more drive signals including a same bias as and either a same phase as or a phase 180 degrees different than a phase of one or more other ones of the two or more drive signals.

11. The system according to claim 10, wherein the two or more components are two identical circuits placed as mirror images of each other on the chip.

12. The system according to claim 11, wherein the two or more drive signals are a first drive signal and a second drive signal respectively driving a same port on each of the two identical circuits, the first drive signal and the second drive signal having a same bias and a same phase.

13. The system according to claim 10, wherein the two or more components are four identical circuits placed on the chip.

14. The system according to claim 13, wherein the two or more drive signals are two first drive signals and two second drive signals that drive a same port on each of the four circuits.

15. The system according to claim 14, wherein the first drive signals, having a same bias and phase, drive a first set of diagonal ports and the second drive signals, having a same bias and a different phase from the first drive signals, drive a second set of diagonal ports.

16. The system according to claim 10, wherein the two or more components are two ports placed symmetrically on the chip along a node associated with a chip mode frequency of interest.

17. The system according to claim 16, wherein the two or more drive signals are a first drive signal and a second drive signal respectively driving each of the two ports, the first drive signal and the second drive signal having a same bias and a different phase.