Stacked bit line dual word line nonvolatile memory

• US 8,975,122 B2
• Filed: 01/06/2014
• Issued: 03/10/2015
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US14/148,155
• Publication Number:
  US 20140120665A1
• Time in Patent Office: 428 Days
• Field of Search: 438/131, 257/209, 257/E23.147, 257/E29.166
• US Class Current: 438/131
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Claims

1. A manufacture method of a semiconductor device, comprising:

providing a substrate;

forming first and second conductive lines over the substrate;

forming a first plug coupled to the first conductive line, and orthogonal to the first conductive line and the substrate;

forming a second plug coupled to the second conductive line, and orthogonal to the second conductive line and the substrate;

forming a first memory cell disposed on a first sidewall beside the first plug, the first sidewall being orthogonal to the substrate; and

forming a second memory cell disposed on a second sidewall beside the second plug, the second sidewall being orthogonal to the substrate, wherein the first memory cell is over the second memory cell.

2. The manufacture method of claim 1, wherein the first and second conductive lines are arranged in respective first and second levels above the substrate.

3. The manufacture method of claim 1, wherein the first and second conductive lines comprise material having a conductivity type opposite a conductivity type of material of the first and second plugs.

4. The manufacture method of claim 3, wherein the first and second conductive lines comprise polysilicon having a first conductivity type, and the first and second plugs comprise polysilicon having a second conductivity type opposite the first conductivity type.

5. The manufacture method of claim 1, wherein the second conductive line is directly above the first conductive line.

6. The manufacture method of claim 1, wherein the first memory cell and the second memory cell comprise non-volatile memory cells.

7. The manufacture method of claim 1, wherein the first memory cell and the second memory cell comprise anti-fuse elements.

8. A manufacture method of a semiconductor device, comprising:

forming a first conductive line;

forming a second conductive line orthogonal to the first conductive line;

forming a plug coupled to the first conductive line, and orthogonal to the first and second conductive lines;

forming a memory cell disposed on a sidewall beside the plug, and between the second conductive line and the plug; and

wherein the second conductive line comprises polysilicon having a first conductivity type, and the plug comprises polysilicon having a second conductivity type opposite the first conductivity type.

9. The manufacture method of claim 8, wherein the second conductive line is above the first conductive line.

10. The manufacture method of claim 8, wherein the second conductive line comprises material having a conductivity type opposite a conductivity type of material of the plug.

11. The manufacture method of claim 8, wherein the memory cell comprises a non-volatile memory cell.

12. The manufacture method of claim 8, wherein the memory cell comprises an anti-fuse element.

13. A method of fabricating an arrangement of nonvolatile memory devices, the method comprising:

(a) providing a semiconductor substrate;

(b) forming an oxide layer;

(c) forming a plurality of word lines above the oxide layer;

(d) forming a plurality of bit lines above the oxide layer;

(e) etching a plurality of via holes formed between the plurality of word lines and the plurality of bit lines;

(f) forming a memory material disposed beside the plurality of bit lines and in electrical contact with the plurality of bit lines, the memory material forming a plurality of side wall memory elements beside the bit lines; and

(g) forming a plurality of via plugs in electrical communication with the plurality of word lines and in electrical communication with the plurality of side wall memory elements.

14. The method of fabricating an arrangement of nonvolatile memory devices according to claim 13, wherein the bit lines are formed from polysilicon having a first type of background impurity and the via plugs are formed from polysilicon having a second type of background impurity opposite to the first type.

15. The method of fabricating an arrangement of nonvolatile memory devices according to claim 14, wherein the first type of background impurity is N-type and the second type of background impurity is P-type.

16. The method of fabricating an arrangement of nonvolatile memory devices according to claim 15, wherein the first type of background impurity is P-type and the second type of background impurity is N-type.

17. The method of fabricating an arrangement of nonvolatile memory devices according to claim 14, wherein the step of forming a plurality of word lines further comprises the step of forming a plurality of pairs of word lines.

18. The method of fabricating an arrangement of nonvolatile memory devices according to claim 17, wherein the pairs of word lines are disposed on different horizontal planes.

19. The method of fabricating an arrangement of nonvolatile memory devices according to claim 18, wherein the bit lines are formed from polysilicon having a first type of background impurity and the via plugs are formed from polysilicon having a second type of background impurity opposite to the first type.