Controlling the shape of source/drain regions in FinFETs

• US 8,975,144 B2
• Filed: 11/30/2012
• Issued: 03/10/2015
• Est. Priority Date: 09/29/2009
• Status: Active Grant

• Current Assignee: Parabellum Strategic Opportunities Fund LLC (Parabellum Capital LLC)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kwok, Tsz-Mei, Su, Chien-Chang, Chen, Kuan-Yu, Sung, Hsueh-Chang, Lin, Hsien-Hsin
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US13/691,093
• Publication Number:
  US 20130089959A1
• Time in Patent Office: 830 Days
• Field of Search: None
• US Class Current: 438/300
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Claims

1. A method comprising:

forming a fin field-effect transistor (FinFET) comprising;

forming a semiconductor fin over and adjacent insulation regions, wherein the;

forming a gate dielectric on a top surface, and extending on sidewalls, of the semiconductor fin;

forming a gate electrode on the gate dielectric; and

forming a source/drain region over the insulation regions and adjoining the semiconductor fin, wherein the forming the source/drain region comprises;

forming a first semiconductor region comprising silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region, and wherein the first semiconductor region comprises an up-slant facet and a down-slant facet; and

forming a second semiconductor region comprising silicon and the element, wherein the element has a second atomic percentage in the second semiconductor region with the second atomic percentage being lower than the first atomic percentage, wherein the second semiconductor region comprises a first portion on the up-slant facet and having a first thickness, and wherein a second portion of the second semiconductor region on the down-slant facet has a second thickness smaller than the first thickness.

2. The method of claim 1, wherein, before the step of forming the source/drain region, the semiconductor fin comprises a portion not covered by the gate dielectric and the gate electrode, and wherein the method further comprises:

removing the portion of the semiconductor fin not covered by the gate dielectric and the gate electrode to form a recess;

performing the step of forming the first semiconductor region in the recess using an epitaxial growth; and

performing the step of forming the second semiconductor region using an additional epitaxial growth.

3. The method of claim 1 further comprising siliciding at least a top portion of the second semiconductor region.

4. The method of claim 3, wherein the second semiconductor region is fully silicided.

5. The method of claim 3, wherein a bottom portion of the second semiconductor region is un-silicided.

6. The method of claim 1, wherein the second atomic percentage is lower than the first atomic percentage by greater than about five percent.

7. The method of claim 1, wherein the second thickness is less than 20 percent of the first thickness.

8. The method of claim 1, wherein there is substantially no second portion of the second semiconductor region on the down-slant facet.

9. The method of claim 1, wherein the up-slant facet and the down-slant facet are on (111) planes.

10. The method of claim 1, wherein the down-slant facet and top surfaces of the insulation regions form an angle equal to about 54.7 degrees.

11. A method comprising:

forming two shallow trench isolation (STI) regions in a silicon substrate and facing each other, with a portion of the silicon substrate therebetween; and

forming a silicon fin over, and horizontally between, the two STI regions;

forming a gate dielectric on a top surface, and extends on sidewalls, of the silicon fin;

forming a gate electrode on the gate dielectric;

removing a portion of the silicon fin not covered by the gate dielectric to form a recess;

epitaxially growing a first SiGe region having a first germanium atomic percentage in the recess, wherein the first SiGe region has an up-slant facet on a (111) plane, and a down-slant facet on an additional (111) plane;

epitaxially growing a second SiGe region having a second germanium atomic percentage lower than the first germanium atomic percentage, wherein the second SiGe region contacts the up-slant facet, and wherein substantially none of the second SiGe region is formed on the down-slant facet; and

siliciding at least a portion of the second SiGe region.

12. The method of claim 11, wherein the second SiGe region is fully silicided.

13. The method of claim 11, wherein a bottom portion of the second SiGe region is un-silicided.

14. The method of claim 11, wherein the second germanium atomic percentage is lower than the first germanium atomic percentage by greater than about five percent.

15. The method of claim 11, wherein the down-slant facet and top surfaces of the two STI regions form an angle equal to about 54.7 degrees.

16. A method comprising:

epitaxially growing a first SiGe region having a first germanium atomic percentage from a space between two shallow trench isolation (STI) regions, wherein the first SiGe region has an up-slant facet on a (111) plane, and a down-slant facet on an additional (111) plane; and

epitaxially growing a second SiGe region having a second germanium atomic percentage lower than the first germanium atomic percentage, wherein the second SiGe region contacts the up-slant facet, and wherein substantially none of the second SiGe region is formed on the down-slant facet.

17. The method of claim 16, wherein the first SiGe region is grown from a level lower than top surfaces of the two STI regions, and wherein the up-slant facet are higher than the top surfaces of the two STI regions.

18. The method of claim 16 further comprising siliciding at least a portion of the second SiGe region.

19. The method of claim 18, wherein a top portion of the second SiGe region on is fully silicided, and wherein a silicide formed the down-slant facet is substantially free from silicide.

20. The method of claim 16 comprising forming a fin field-effect transistor (FinFET), wherein the first SiGe region and the second SiGe region form a source or drain region of the FinFET.