Methods for optical proximity correction in the design and fabrication of integrated circuits

• US 8,975,195 B2
• Filed: 02/01/2013
• Issued: 03/10/2015
• Est. Priority Date: 02/01/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Lukanc, Todd, Clifford, Christopher Heinz, Coskun, Tamer
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US13/757,286
• Publication Number:
  US 20140220786A1
• Time in Patent Office: 767 Days
• Field of Search: 438/780, 438/942, 438/948, 716/53, 716/54, 716/55, 430/5, 382/144
• US Class Current: 438/780
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/948 Radiation resist

Abstract

A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.

Claims

1. A method of manufacturing an optical lithography mask, the method comprising the steps of:

designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the step of designing the optical photomask comprises;

providing a patterned layout design comprising a plurality of polygons that correspond with the pre-pattern opening;

correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design;

converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons; and

biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design; and

manufacturing the optical photomask in a mask writer tool using the biased, mask writer-compatible layout design as a template for the optical photomask.

2. The method of claim 1, wherein providing the patterned layout design comprises providing a computer-generated patterned layout design.

3. The method of claim 1, wherein correcting the pattern layout design using OPC comprises accounting for proximity effect errors.

4. The method of claim 3, wherein accounting for proximity effect errors comprises accounting for errors introduced within a few microns of a respective polygon of the plurality of polygons.

5. The method of claim 1, wherein converting the corrected patterned layout design into a mask writer-compatible format comprises accounting for mask writer electron beam process variations.

6. The method of claim 1, wherein biasing each polygon in the plurality of polygons is performed coterminously with converting the corrected patterned layout design into a mask writer-compatible format.

7. The method of claim 1, wherein the optical photomask is designed to form the pre-pattern opening using extreme ultraviolet (EUV) light.

8. The method of claim 7, wherein biasing each polygon in the plurality of polygons comprises compensating for EUV flare.

9. The method of claim 1, wherein providing the patterned layout design comprises providing at least one chip design and at least one Kerf design.

10. The method of claim 1, wherein correcting the patterned layout design using OPC comprises separately correcting the at least one chip design and the at least one Kerf design.

11. The method of claim 1, wherein biasing each polygon in the plurality of polygons with the bias is performed subsequent to correcting the patterned layout design using OPC.

12. A method for fabricating an integrated circuit, the method comprising:

providing semiconductor substrate comprising a silicon material;

forming a photoresist layer over the semiconductor substrate;

providing an optical photomask mask, wherein providing the optical lithography mask comprises the steps of;

designing the optical photomask for forming a pre-pattern opening in the photoresist layer on the semiconductor substrate, wherein the step of designing the optical photomask comprises;

providing a patterned layout design comprising a plurality of polygons that correspond with the pre-pattern opening;

correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design;

converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons; and

biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design; and

manufacturing the optical photomask in a mask writer tool using the biased, mask writer-compatible layout design as a template for the optical photomask;

disposing the optical photomask over the photoresist layer; and

directing a light source through the photomask so as to expose a portion of the photoresist layer to the light source.

13. The method of claim 12, wherein providing the patterned layout design comprises providing a computer-generated patterned layout design.

14. The method of claim 12, wherein correcting the pattern layout design using OPC comprises accounting for proximity effect errors.

15. The method of claim 14, wherein accounting for proximity effect errors comprises accounting for errors introduced within a few microns of a respective polygon of the plurality of polygons.

16. The method of claim 12, wherein converting the corrected patterned layout design into a mask writer-compatible format comprises accounting for mask writer electron beam process variations.

17. The method of claim 12, wherein biasing each polygon in the plurality of polygons is performed coterminously with converting the corrected patterned layout design into a mask writer-compatible format.

18. The method of claim 12, wherein the optical photomask is designed to form the pre-pattern opening using extreme ultraviolet (EUV) light.

19. The method of claim 18, wherein biasing each polygon in the plurality of polygons comprises compensating for EUV flare.

20. A method of manufacturing an optical lithography mask, the method comprising the steps of:

designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the step of designing the optical photomask comprises;

providing a patterned layout design comprising a plurality of polygons that correspond with the pre-pattern opening; and

converting the patterned layout design into a mask writer tool-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons; and

manufacturing the optical photomask in a mask writer tool using the mask writer tool-compatible layout design as a template for the optical photomask, wherein the step of manufacturing the optical photomask comprises correcting for flare by altering an intensity of the mask writer tool during a mask write process to one or more polygon images of the plurality of polygons.