Gate stacks including Ta;Si;O for MOSFETS

• US 8,975,706 B2
• Filed: 12/19/2013
• Issued: 03/10/2015
• Est. Priority Date: 08/06/2013
• Status: Expired due to Fees

• Current Assignee: Intermolecular Incorporated (Merck & Co., Inc.)
• Original Assignee: Intermolecular Incorporated (Merck & Co., Inc.)
• Inventors: Ahmed, Khaled, Greer, Frank
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Rahim, Nilufa
• Application Number:
  US14/135,381
• Publication Number:
  US 20150041912A1
• Time in Patent Office: 446 Days
• Field of Search: 257/213, 257/369, 257/410, 257/411, 257/E21.212, 257/E21.409, 257/E27.06, 257/E29.06, 257/E29.051, 257/E51.006, 438/591, 438/151, 438/257, 438/197
• US Class Current: 257/369
• CPC Class Codes: H01L 21/0215 the material containing tantalum, e.g. TaSiOx
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.

Claims

1. A method of forming a FET assembly, the method comprising:

providing a channel region;

forming an interface layer over the channel region; and

forming a dielectric layer over the interface layer such that the interface layer is disposed between the channel region and the dielectric layer,

the dielectric layer comprising a tantalum silicon oxide,

wherein an atomic ratio of silicon to a total amount of silicon and tantalum is less than 0.05,

wherein forming the dielectric layer comprises;

supplying a tantalum containing precursor into a deposition chamber such that the tantalum containing precursor adsorbs on a surface of the interface layer,

after the tantalum containing precursor is adsorbed on the surface of the interface layer, supplying a silicon containing precursor into the deposition chamber such that the silicon containing precursor adsorbs on the surface of the interface layer already having the tantalum containing precursor previously adsorbed on the surface of the interface layer,

wherein, after supplying the silicon containing precursor into the deposition chamber an amount of the silicon containing precursor adsorbed on the surface of the interface layer is less than an amount of the tantalum containing precursor adsorbed on the surface of the interface layer, and

after the tantalum containing precursor and the silicon containing precursor are adsorbed on the surface of the interface layer, supplying an oxygen containing reagent into the deposition chamber such that the oxygen containing reagent reacts with the silicon containing precursor and the tantalum containing precursor adsorbed on the surface of the interface layer thereby forming the tantalum silicon oxide.

2. The method of claim 1, further comprising forming a capping layer over the dielectric layer.

3. The method of claim 2, wherein the capping layer comprises titanium nitride.

4. The method of claim 2, wherein after forming the dielectric layer and until forming the capping layer the dielectric layer is maintained in an oxygen free environment.

5. The method of claim 1, wherein after forming the interface layer and until forming the dielectric layer the interface layer is maintained in an oxygen free environment.

6. The method of claim 1, wherein the interface layer is formed using an ALD technique.

7. The method of claim 1, further comprising, prior to forming the interface layer, cleaning a surface of the channel region used to form the interface layer thereon.

8. The method of claim 7, wherein the surface of the channel region is cleaned using atomic hydrogen.

9. The method of claim 1, wherein the interface layer comprises silicon.

10. The method of claim 1, wherein the channel region comprises one of indium gallium arsenide, indium phosphate, germanium, germanium tin, or gallium antimony.

11. The method of claim 1, wherein the dielectric layer has a thickness of less than 2 nanometers.

12. The method of claim 1, wherein the interface layer has a thickness of less than 0.7 nanometers.