Bias circuit and method of manufacturing the same

• US 8,975,725 B2
• Filed: 12/01/2009
• Issued: 03/10/2015
• Est. Priority Date: 12/04/2008
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hamada, Yasuhiro, Kishimoto, Shuya, Maruhashi, Kenichi
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US13/129,344
• Publication Number:
  US 20110221032A1
• Time in Patent Office: 1,925 Days
• Field of Search: 257/528, 257/531, 257536-538
• US Class Current: 257/531
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/255 Amplifier input adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/423 Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
• CPC Class Codes: H03F 3/195 in integrated circuits

Abstract

A bias circuit according to the present invention includes a resistor layer 2 which is placed above a substrate 1 and connected to a ground potential, and a conductor 4 for forming an inductor 5 placed above the resistor layer 2. Further, a manufacturing method of the bias circuit according to the present invention generates the resistor layer 2 above the substrate 1 and is connected to the ground potential, and generates the conductor 4 for forming the inductor 5 above the resistor layer 2. The present invention can provide a bias circuit and a manufacturing method of the bias circuit that enables easy integration on a semiconductor substrate and prevents parasitic oscillation.

Claims

1. A high frequency amplifier comprising:

an FET amplifying a high frequency signal supplied to a gate and outputting an amplified high frequency signal from a drain;

a first bias circuit supplying a gate bias to the gate of the FET; and

a second bias circuit supplying a drain bias to the drain of the FET,

wherein each of the first bias circuit and the second bias circuit comprise;

a resistor layer that is placed over a substrate and connected to a ground potential;

an insulator that is placed above the resistor layer;

a conductor that is placed above the insulator and forms an inductor; and

a shunt RC circuit that is formed between an input terminal and an output terminal of the inductor,

wherein the shunt RC circuit comprises a parasitic capacitance that is generated by the conductor and the resistor layer, and a parasitic resistance that is generated by an eddy current induced in the resistor layer when an alternating current signal is applied to the conductor,

wherein an output terminal of the first bias circuit is connected to the gate of the FET and the gate bias is supplied to an input terminal of the first bias circuit, and

wherein an output terminal of the second bias circuit is connected to the drain of the FET and the drain bias is supplied to an input terminal of the second bias circuit.

2. The high frequency amplifier according to claim 1, wherein an input terminal of the inductor is connected to a power supply, and an output terminal of the inductor is connected to a power supply unit of an integrated circuit.

3. The high frequency amplifier according to claim 1, wherein the inductor is formed by connecting each of a plurality of metal layers by a via.

4. The high frequency amplifier according to claim 1, wherein the inductor is formed by connecting a polysilicon layer and the plurality of metal layers by a via.

5. The high frequency amplifier according to claim 1, wherein the wire of the inductor is formed of gold.

6. The bias circuit according to claim 1, wherein the inductor is placed below a pad which supplies bias and is connected to the pad by the via.

7. The high frequency amplifier according to claim 1, wherein the substrate is silicon.

8. The high frequency amplifier according to claim 1, wherein the substrate is a Silicon-on-Insulator substrate.

9. The high frequency amplifier according to claim 1, wherein the substrate is a compound semiconductor.

10. The high frequency amplifier according to claim 1, wherein the substrate is ceramic.

11. The high frequency amplifier according to claim 1, wherein the resistor layer is formed in a silicon IC process.

12. The high frequency amplifier according to claim 1, wherein the resistor layer is a thin metal film resistor.

13. The high frequency amplifier according to claim 1, wherein the insulator placed above the resistor is silicon nitride.

14. The high frequency amplifier according to claim 1, wherein the insulator placed above the resistor layer is oxide silicon.

15. The high frequency amplifier according to claim 1, wherein the resistor layer is an unpatterned layer.