Data and power system based on CMOS bridge
First Claim
1. A signal processing circuit comprising:
- a CMOS bridge rectifier circuit including;
a first input terminal and a second input terminal for receiving a rectangular wave form that includes a data sequence;
a first output terminal and a second output terminal for providing a rectified dc output voltage; and
a first data output terminal connected to one of the first and the second input terminals, and a second data output terminal connected to one of the first and the second output terminals, wherein the data output terminals provide an output signal representative of the data sequence.
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Accused Products
Abstract
A signal processing circuit includes an input inverter and an output inverter. Each inverter has a signal input for receiving an input rectangular signal, a signal output for providing an inverted output rectangular signal, and a pair of voltage outputs for developing a rectified dc output voltage. A first circuit input terminal is connected to the output of the input inverter and the input of the output inverter. A second circuit input terminal is connected to the input of the input inverter and the output of the output inverter, wherein the signal input terminals receive an input signal having a data component. A pair of supply voltage output terminals is connected to the voltage output terminals of the inverters for providing a rectified dc supply voltage output. A first circuit output terminal is connected to one of the supply voltage output terminals, and a second circuit output terminal connected to the second circuit input terminal, wherein the circuit output terminals provide an output signal including the data component.
60 Citations
25 Claims
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1. A signal processing circuit comprising:
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a CMOS bridge rectifier circuit including; a first input terminal and a second input terminal for receiving a rectangular wave form that includes a data sequence; a first output terminal and a second output terminal for providing a rectified dc output voltage; and a first data output terminal connected to one of the first and the second input terminals, and a second data output terminal connected to one of the first and the second output terminals, wherein the data output terminals provide an output signal representative of the data sequence. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of providing data and power in a medical implant, the method comprising:
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applying a rectangular wave input signal between a first input terminal and a second input terminal, a first switch coupled between the first input terminal and a first node, a second switch coupled between the second input terminal and the first node, the first node coupled to a first output terminal, a third switch coupled between the first input terminal and a second node, a fourth switch coupled between the second input terminal and the second node;
the second node coupled to a second output terminal, a third output terminal coupled to the second input terminal, and a fourth output terminal coupled to the second node;wherein the first switch and fourth switch are gated on when the input signal is of a first polarity; and
wherein the second switch and the third switch are gated on when the input signal is of a second polarity opposite the first polarity so that the first and second output terminals provide a dc voltage, and the third and fourth output terminals provide a data component. - View Dependent Claims (14, 15, 16, 17)
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18. A method of providing data and power in a medical implant, the method comprising:
applying a rectangular wave form that includes a data sequence across a first input terminal and a second input terminal of a CMOS bridge rectifier, the CMOS bridge rectifier including a first output terminal and a second output terminal for providing a rectified dc output voltage, wherein a first data output terminal connected to one of the first and the second input terminals, and a second data output terminal connected to one of the first and the second output terminals, the data output terminals providing an output signal representative of the data sequence. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
Specification