Level shift circuit utilizing resistance in semiconductor substrate
First Claim
1. A level shift circuit, comprising:
- a first series circuit wherein a first resistor in a semiconductor substrate, a first switching element connected to an input terminal for inputting a first level shift input signal, and a first level shift output terminal for outputting a first level shift output signal are connected in series;
a second series circuit wherein a second resistor in a semiconductor substrate, a second switching element connected to an input terminal for inputting a second level shift input signal, and a second level shift output terminal for outputting a second level shift output signal are connected in series;
rise detector circuits, connected to the first series circuit and second series circuit and into which are input the first level shift output signal and second level shift output signal output from the first series circuit and second series circuit respectively, that compare the rising potential of the first level shift output signal and second level shift output signal with a predetermined threshold value, and output a first output signal and second output signal, which are pulse outputs of a constant duration, when the threshold value is exceeded;
a third switching element connected in parallel to the first resistor, wherein a source terminal of the third switching element is connected to a power source potential, a drain terminal of the third switching element is connected to the first level shift output terminal, and a gate terminal of the third switching element is connected to the rise detector circuits; and
a fourth switching element connected in parallel to the second resistor, wherein a source terminal of the fourth switching element is connected to a power source potential, a drain terminal of the fourth switching element is connected to the second level shift output terminal, and a gate terminal of the fourth switching element is connected to the rise detector circuits, whereinthe third switching element is turned on by the first output signal from the rise detector circuits, and the fourth switching element is turned on by the second output signal from the rise detector circuits.
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Abstract
A level shift circuit does not affect delay time, regardless of the size of resistor resistance value. The level shift circuit includes first and second series circuits wherein first and second resistors and first and second switching elements are connected in series, rise detector circuits that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements connected in parallel to the first and second resistors respectively. The gate terminals of the third and fourth switching elements are connected to the rise detector circuits, and the third and fourth switching elements are turned on by the first and second output signals respectively.
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Citations
11 Claims
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1. A level shift circuit, comprising:
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a first series circuit wherein a first resistor in a semiconductor substrate, a first switching element connected to an input terminal for inputting a first level shift input signal, and a first level shift output terminal for outputting a first level shift output signal are connected in series; a second series circuit wherein a second resistor in a semiconductor substrate, a second switching element connected to an input terminal for inputting a second level shift input signal, and a second level shift output terminal for outputting a second level shift output signal are connected in series; rise detector circuits, connected to the first series circuit and second series circuit and into which are input the first level shift output signal and second level shift output signal output from the first series circuit and second series circuit respectively, that compare the rising potential of the first level shift output signal and second level shift output signal with a predetermined threshold value, and output a first output signal and second output signal, which are pulse outputs of a constant duration, when the threshold value is exceeded; a third switching element connected in parallel to the first resistor, wherein a source terminal of the third switching element is connected to a power source potential, a drain terminal of the third switching element is connected to the first level shift output terminal, and a gate terminal of the third switching element is connected to the rise detector circuits; and a fourth switching element connected in parallel to the second resistor, wherein a source terminal of the fourth switching element is connected to a power source potential, a drain terminal of the fourth switching element is connected to the second level shift output terminal, and a gate terminal of the fourth switching element is connected to the rise detector circuits, wherein the third switching element is turned on by the first output signal from the rise detector circuits, and the fourth switching element is turned on by the second output signal from the rise detector circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification