Amplifiers with improved isolation
First Claim
1. An apparatus comprising:
- a gain transistor configured to receive an input signal and to provide an amplified signal;
a first cascode transistor coupled between the gain transistor and an intermediate node, the first cascode transistor having a first gate and configured to be enabled based on a bias voltage received at the first gate;
a second cascode transistor coupled between the intermediate node and an output node, the second cascode transistor having a second gate that is coupled to the first gate, the second cascode transistor configured to be enabled based on receiving the bias voltage at the second gate and configured to provide an output signal; and
a shunt transistor coupled between the intermediate node and ground.
1 Assignment
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Accused Products
Abstract
Amplifiers with improved isolation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier having a gain transistor, first and second cascode transistors, and a shunt transistor. The gain transistor receives an input signal and provides an amplified signal. The first cascode transistor is coupled between the gain transistor and an intermediate node and receives the amplified signal. The second cascode transistor is coupled between the intermediate node and an output node and provides an output signal. The shunt transistor is coupled between the intermediate node and circuit ground. The first and second cascode transistors are enabled to provide the output signal. The shunt transistor is (i) disabled when the cascode transistors are enabled and (ii) enabled to short the intermediate node to circuit ground when the cascode transistors are disabled.
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Citations
20 Claims
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1. An apparatus comprising:
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a gain transistor configured to receive an input signal and to provide an amplified signal; a first cascode transistor coupled between the gain transistor and an intermediate node, the first cascode transistor having a first gate and configured to be enabled based on a bias voltage received at the first gate; a second cascode transistor coupled between the intermediate node and an output node, the second cascode transistor having a second gate that is coupled to the first gate, the second cascode transistor configured to be enabled based on receiving the bias voltage at the second gate and configured to provide an output signal; and a shunt transistor coupled between the intermediate node and ground. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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amplifying an input signal via a gain transistor to provide an amplified signal; buffering the amplified signal based on a first operating mode via a first cascode transistor coupled to an intermediate node and a second cascode transistor coupled to the intermediate node to provide an output signal, wherein, during the first operating mode, the first cascode transistor is enabled, a shunt transistor is disabled, and the second cascode transistor is enabled and provides the output signal; and shorting the intermediate node to ground via the shunt transistor based on a second operating mode. - View Dependent Claims (14, 15, 16, 17)
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18. An apparatus comprising:
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means for providing an amplified signal based on an input signal; first means for buffering the amplified signal, the first means for buffering coupled between the means for providing the amplified signal and an intermediate node the first means for buffering configured to be enabled based on a bias voltage received at a first gate; second means for buffering the amplified signal, the second means for buffering coupled between the intermediate node and an output node and configured to be enabled based on the bias voltage received at a second gate that is coupled to the first gate; and means for shorting the intermediate node to ground. - View Dependent Claims (19, 20)
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Specification