Semiconductor apparatus

• US 8,976,567 B2
• Filed: 12/19/2012
• Issued: 03/10/2015
• Est. Priority Date: 08/17/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Dong Keun
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US13/720,706
• Publication Number:
  US 20140050021A1
• Time in Patent Office: 811 Days
• Field of Search: 365/148, 365/163, 365/185.11, 365/189.04, 365/189.19, 365/220, 365/230.03
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.

Claims

1. A semiconductor apparatus having a core area and a peripheral area, comprising:

a first bank group including a plurality of banks stacked with each other and arranged at the core area, wherein the plurality of banks of the first bank group are arranged in a first direction;

a second bank group including a plurality of banks stacked with each other and arranged at the core area, wherein the plurality of banks of the second bank group are arranged in the first direction;

a write driver and a sense amplifier connected to the plurality of banks of the first and second bank groups; and

a verify sense amplifier connected to the write driver and configured to verify a write operation performed in any one bank selected among the plurality of banks of the first or second bank groups,

wherein the write driver and the verify sense amplifier are arranged between the first and second bank groups, the sense amplifier are arranged between the second bank group and the peripheral area, the first and second banks include a plurality of mats, respectively and the second bank group is located between the verify sense amplifier and the sense amplifier.

2. The semiconductor apparatus according to claim 1, further comprising:

a plurality of write global bit lines connected to one or more bit lines arranged in the plurality of banks and configured to transmit write data during a write operation; and

a plurality of read global bit lines connected to one or more bit lines arranged in the plurality of banks and configured to transmit read data during a read operation.

3. The semiconductor apparatus according to claim 2, wherein the write driver is connected to the plurality of write global bit lines, and generates a write driving signal to transmit write data inputted from outside through any one write global bit line selected among the plurality of write global bit lines, when a write command is inputted from outside or a verification output signal is inputted from the verify sense amplifier.

4. The semiconductor apparatus according to claim 2, wherein the verify sense amplifier is connected to the plurality of write global bit lines, receives write data of a previously-performed write operation through any one write global bit line selected among the plurality of write global bit lines, verifies whether or not the received write data is input write data, and transmits a verification output signal to the write driver.

5. The semiconductor apparatus according to claim 2, wherein the sense amplifier is connected to the plurality of read global bit lines, receives read data through any one read global bit line selected among the plurality of read global bit lines when a read command is inputted from outside, amplifies the received read data, and outputs the amplified data to outside.

6. The semiconductor apparatus according to claim 2, further comprising:

a write global bit line switch arranged among the write driver, the verify sense amplifier, and the plurality of banks, and configured to select any one of the plurality of write global bit lines connected to the plurality of banks; and

a read global bit line switch arranged between the sense amplifier and the plurality of banks, and configured to select any one of the plurality of read global bit lines connected to the plurality of banks.