Process corner sensor for bit-cells

• US 8,976,574 B2
• Filed: 03/13/2013
• Issued: 03/10/2015
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Ahmed, Fahad, Abu-Rahma, Mohamed Hassan, Jin, Peng
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/799,408
• Publication Number:
  US 20140269017A1
• Time in Patent Office: 727 Days
• Field of Search: 365/154, 365/205, 365/156
• US Class Current: 365/154
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.

Claims

1. An integrated circuit, comprising:

a plurality of bit-cells arranged to store data; and

a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner, wherein the sensor comprises

two cross-coupled inverters, each of the cross-coupled inverters comprising a p-channel pull-up transistor and an n-channel pull-down transistor,

a first access transistor configured to connect a first bit-line to an input of a first one of the inverters when a word-line is asserted, and

a second access transistor configured to a connect a second bit-line to an input of a second one of the inverters when the word-line is asserted; and

circuitry configured to;

sense a first current flowing through one of the p-channel pull-up transistors with each of the first and second bit-lines pulled-down,

sense a second current flowing through one of the n-channel pull-down transistors with each of the first and second bit-lines pulled-up,

determine whether the bit-cells are operating at the process corner based on the first and second sensed currents, and

sense the second current flowing through said one of the n-channel pull-down transistors with a source of an other n-channel pull-down transistor pulled-up.

2. The integrated circuit of claim 1 further comprising circuitry configured to determine whether the bit-cells are operating at the process corner based on the sensor output.

3. The integrated circuit of claim 2 wherein the circuitry is further configured to sense current output from the sensor and determine whether the bit-cells are operating at the process corner based on the sensed current.

4. The integrated circuit of claim 2 wherein the circuitry is further configured to provide assist to the bit-cells if the circuitry determines that the bit-cells are operating at the process corner.

5. The integrated circuit of claim 4 wherein the circuitry is further configured to provide read assist to the bit-cells if the circuitry determines that the process corner is a fast-slow (FS) corner.

6. The integrated circuit of claim 4 wherein the circuitry is further configured to provide write assist to the bit-cells if the circuitry determines that the process corner is a slow-fast (SF) corner.

7. An integrated circuit, comprising:

a plurality of bit-cells arranged to store data; and

sensor means for generating an output to determine whether the bit-cells are operating at a process corner, wherein the sensor means comprises

two cross-coupled inverters, each of the cross-coupled inverters comprising a p-channel pull-up transistor and an n-channel pull-down transistor,

a first access transistor configured to connect a first bit-line to an input of a first one of the inverters when a word-line is asserted, and

a second access transistor configured to a connect a second bit-line to an input of a second one of the inverters when the word-line is asserted; and

circuit means for determining whether the bit-cells are operating at the process corner configured to;

sense a first current flowing through one of the p-channel pull-up transistors with each of the first and second bit-lines pulled-down,

sense a second current flowing through one of the n-channel pull-down transistors with each of the first and second bit-lines pulled-up,

determine whether the bit-cells are operating at the process corner based on the first and second sensed currents, and

sense the second current flowing through said one of the n-channel pull-down transistors with a source of an other n-channel pull-down transistor pulled-up.

8. The integrated circuit of claim 7 further comprising circuit means for determining whether the bit-cells are operating at the process corner based on the output from the sensor means.

9. The integrated circuit of claim 8 wherein the circuit means comprises means for sensing current output from the sensor means, the circuit means being configured to determine whether the bit-cells are operating at the process corner based on the sensed current.

10. The integrated circuit of claim 9 wherein the circuit means is configured to provide assist to the bit-cells if the circuit means determines that the bit-cells are operating at the process corner.

11. The integrated circuit of claim 10 wherein the circuit means is further configured to provide read assist to the bit-cells if the circuit means determines that the process corner is a fast-slow (FS) corner.

12. The integrated circuit of claim 10 wherein the circuit means is further configured to provide write assist to the bit-cells if the circuit means determines that the process corner is a slow-fast (SF) corner.

13. A method of testing a plurality of bit-cells arranged to store data on an integrated circuit, the method comprising:

generating from a sensor an output for determining whether the bit-cells are operating at a process corner, wherein the sensor comprises

two cross-coupled inverters, each of the cross-coupled inverters comprising a p-channel pull-up transistor and an n-channel pull-down transistor,

a first access transistor configured to connect a first bit-line to an input of a first one of the inverters when a word-line is asserted, and

a second access transistor configured to a connect a second bit-line to an input of a second one of the inverters when the word-line is asserted; and

determining whether the bit-cells are operating at the process corner by

sensing a first current flowing through one of the p-channel pull-up transistors with each of the first and second bit-lines pulled-down, and

sensing a second current flowing through one of the n-channel pull-down transistors with each of the first and second bit-lines pulled-up, wherein the second current flows through said one of the n-channel pull-down transistors with a source of the other n-channel pull-down transistor pulled-up, and wherein the determining is based on the first and second sensed currents.

14. The method of claim 13 further comprising determining whether the bit-cells are operating at the process corner based on the sensor output.

15. The method of claim 14 wherein the determining of whether the bit-cells are operating at the process corner comprises sensing current output from the sensor and determining whether the bit-cells are operating at the process corner based on the sensed current.

16. The method of claim 14 further comprising providing assist to the bit-cells if the bit-cells are operating at the process corner.

17. The method of claim 16 wherein the providing of the assist comprises providing read assist to the bit-cells if the process corner is a fast-slow (FS) corner.

18. The integrated circuit of claim 16 wherein the providing of the assist comprises providing write assist to the bit-cells if the process corner is a slow-fast (SF) corner.