NVSRAM cells with voltage flash charger

• US 8,976,588 B2
• Filed: 10/28/2013
• Issued: 03/10/2015
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US14/064,222
• Publication Number:
  US 20140119120A1
• Time in Patent Office: 498 Days
• Field of Search: 365/185.08, 365/185.24
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

The present invention discloses two preferred embodiments of a 12T NVSRAM cell with a flash-based Charger and a pseudo 10T NVSRAM cell with one shared Flash-based Charger. The Flash-based Charger can be made of a 2-poly floating-gate type or a 1-poly charge-trapping SONOS/MONOS flash type, regardless of PMOS type or NMOS type. In an alternative embodiment, the Store operation of above two preferred NVSRAM cell use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower associated with Flash Charger and 2-step SRAM amplification technique to amplify the threshold level difference ΔVt stored in the paired Flash transistors. The ΔVt can be detected as low as 1V when the coupled charges through the Flash charger are sufficient by ramping a gate control of the Flash Charger as high as VPP or by increasing the channel length for the Flash Charger.

Claims

1. A 12T NVSRAM memory cell circuit with a pair of flash-based transistors as a voltage charger, the 12T NVSRAM memory cell comprising:

a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two invertors, each inverter including a PMOS device connected to a first power line and a NMOS device connected to a second power line, the first power line and the second power line being operated between a VDD power supply and ground and being separated from a common Nwell node; and

a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second Select transistor, a first/second Flash transistor, and a first/second Charger transistor connected in series, the first Select transistor and the second Select transistor being gated commonly by a select-gate control line and respectively associated with a first drain terminal coupled to the first data node and a second drain terminal coupled to the second data node, the first and the second Flash transistors being gated commonly by a second word line, the first Charger transistor and the second Charger transistor being gated commonly by a pump word line and respectively associated with a first source terminal and a second source terminal, the first source terminal and the second source terminal being left floating;

wherein the first Charger transistor and the second Charger transistor are configured to ramp the second word line up to the VDD level followed by ramping the pump word line to a high voltage above the VDD level to generate coupling charges to respectively pass a voltage level difference through a first voltage-follower made by the first Flash transistor and the first Select transistor to the first data node and through a second voltage-follower made by the second Flash transistor and the second Select transistor to the second data node, the two cross-coupled inverters are operated to amplify the voltage level difference to a scale of VSS=0V at one of the first data node and the second data node and the VDD level at another one of the first data node and the second data node.

2. The 12T NVSRAM memory cell of claim 1 wherein each of the first Flash transistor and the second Flash transistor is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

3. The 12T NVSRAM memory cell of claim 1 wherein each of the first Charger transistor and the second Charger transistor is a same type as each of the first Flash transistor and the second Flash transistor no matter that is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

4. The 12T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Read and Write operation by setting the first word line to the VDD level if the SRAM cell is selected or to VSS=0V if the SRAM cell is not selected and applying the VDD level to the first power line and VSS to the second power line, while setting the select-gate control line to VSS along with a Don'"'"'t care state for the second word line and the pump word line to isolated each SRAM cell from each corresponding Flash cell.

5. The 12T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a an Erase operation including a preset step by setting both the first data node and the second data node to VSS under a condition of setting the first word line to the VDD level, the first power line to VSS, the second power line to VSS, the select-gate control line to VSS, followed by an erase step by applying a negative high voltage VNN to the second word line to decrease threshold levels of both the first Flash transistor and the second Flash transistor to ≦

−

2V under a FN-channel scheme in less than 5 ms, along with a Don'"'"'t care state for the pump word line.

6. The 12T NVSRAM memory cell of claim 5 wherein the negative high voltage VNN is about −

18V for a 2-poly floating-gate type flash transistor or about −

10V for a 1-poly charge-trapping type flash transistor, and the VDD level is about 1V to 2V.

7. The 12T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

1”

of the SRAM cell with the first data node at the VDD level and the second data node at VSS=0V, the Program operation further including a programming step of applying the VDD level to the select-gate control line and ramping the second word line from VSS to a positive high voltage VPP to use a FN-channel scheme to maintain threshold level of the first Flash transistor and increase threshold level of the second Flash transistor to a positive value along with a Don'"'"'t care state for the pump word line, thereby storing the flash logic state “

0”

in the Flash cell.

8. The 12T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

0”

of the SRAM cell with the first data node at VSS and the second data node at the VDD level, the Program operation further including a programming step of applying the VDD level to the select-gate control line and ramping the second word line from VSS to a positive high voltage VPP to use a FN-channel scheme to increase threshold level of the first Flash transistor to a positive value and maintain threshold level of the second Flash transistor along with a Don'"'"'t care state for the pump word line, thereby storing the flash logic state “

1”

in the Flash cell.

9. The 12T NVSRAM memory cell of claim 8 wherein the positive voltage VPP is about +18V for a 2-poly floating-gate type flash transistor or about +10V for a 1-poly charge-trapping type flash transistor and the VDD level is preferred to be smaller than 2V.

10. The 12T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Recall operation for writing a flash logic state stored in the Flash cell back to the first data node and the second data node under a charge-sensing scheme, the flash logic state including at least a state “

1”

defined by a Vt1 threshold level for the first Flash transistor and a Vt0<

0<

Vt1 threshold level for the second Flash transistor or a state “

0”

defined by a Vt0 threshold level for the first Flash transistor and a Vt1>

0>

Vt0 threshold level for the second Flash transistor.

11. The 12T NVSRAM memory cell of claim 10 wherein the Recall operation for writing a flash logic state “

1”

to the SRAM cell comprises initializing the SRAM cell with the first data node and the second data node, the first bit line and the second bit line, the first power line and the second power line all at VSS=0V by pulsing the first word line to the VDD level, and setting the second word line and the pump word line to VSS, followed by firstly ramping the second power line from VSS to the VDD level, secondly ramping the second word line from VSS to the VDD level, and thirdly ramping the pump word line from VSS to a voltage substantially above the VDD level, and sequentially ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step followed by ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step.

12. The 12T NVSRAM memory cell of claim 11 wherein the Recall operation further comprises setting the select-gate control line to the VDD level plus a threshold level of either the first Select transistor or the second Select transistor.

13. The 12T NVSRAM memory cell of claim 11 wherein firstly ramping the second power line from VSS to the VDD level comprises forming a reversed bias condition for the two Inverters of the SRAM cell to prevent charges in the first data node and the second data node from leaking.

14. The 12T NVSRAM memory cell of claim 11 wherein secondly ramping the second word line from VSS to the VDD level comprises detecting a coupling charge difference between the first Flash transistor and the second Flash transistor due to Vt0<

Vt1.

15. The 12T NVSRAM memory cell of claim 14 wherein thirdly ramping the pump word line from VSS to the voltage substantially above the VDD level comprises keeping gate voltage of the first Charger transistor and the second Charger transistor below a programming voltage VPP of +18V for generating coupling charges in drain nodes of the first Charger transistor and the second Charger transistor, the coupling charges being passed with the coupling charge difference using a voltage-follower operation through the first Flash transistor and the first Select transistor to the first data node with a first level of charges and respectively through the second Flash transistor and the second Select transistor to the second data node with a second level of charges, the first level being higher than the second level due to Vt0<

Vt1.

16. The 12T NVSRAM memory cell of claim 15 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step comprises pulling up the first level of charges at the first data node to substantially the VDD level and pulling up the second level of charges at the second data node to a third level of charges, the third level being lower than the VDD level.

17. The 12T NVSRAM memory cell of claim 16 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step comprises pulling down the third level of charges at the second data node to VSS=0V while maintaining the VDD level at the first data node.

18. The 12T NVSRAM memory cell of claim 16 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step comprises coupling the second word line to a negative bias voltage to turn off both the first Flash transistor and the second Flash transistor.

19. The 12T NVSRAM memory cell of claim 17 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step comprises coupling the second word line to a negative bias voltage below a lowest threshold level to turn off both the first Flash transistor and the second Flash transistor.

20. The 12T NVSRAM memory cell of claim 11 wherein the Recall operation further comprises setting the first word line to the VDD level and resetting the first power line to the VDD level, the second power line to VSS, the select-gate control line to VSS, and the second word line to VSS=0V to return to a SRAM operation with a loaded logic state “

1”

associated with the VDD at the first data node and VSS at the second data node.

21. A paired pseudo-10T NVSRAM memory cell circuit with a shared flash charger, the paired pseudo-10T NVSRAM memory cell comprising:

a first pseudo-10T NVSRAM cell having a first flash source terminal and second flash source terminal;

a second pseudo-10T NVSRAM cell having a third flash source terminal and fourth flash source terminal; and

a first Charger transistor and a second Charger transistor commonly gated by a pump word line, the first Charger transistor having a first charger drain node connected to the first flash source terminal and a first charger source node connected to the third flash source terminal, the second Charger transistor having a second charger drain node connected to the second flash source terminal and a second charger source node connected to the fourth flash source terminal;

wherein the first pseudo-10T NVSRAM cell and the second pseudo-10T NVSRAM cell are configured to be substantially same in a NVSRAM cell structure sharing separately a first common power line and a second common power line respectively operated between a VDD power supply and ground, the NVSRAM cell structure comprising,

a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two invertors, each inverter including a PMOS device connected to the first power line and a NMOS device connected to the second power line, the first power line and the second power line being separated from a common Nwell node; and

a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second Select transistor, a first/second Flash transistor, and a first/second Charger transistor connected in series, the first Select transistor and the second Select transistor being gated commonly by a select-gate control line and respectively associated with a first drain terminal coupled to the first data node and a second drain terminal coupled to the second data node, the first and the second Flash transistors being gated commonly by a second word line, the first Charger transistor and the second Charger transistor being gated commonly by a pump word line and respectively associated with a first source terminal and a second source terminal, the first source terminal and the second source terminal being left floating;

wherein the first/second source node of the first pseudo-10T NVSRAM cell is the first/second flash source terminal and the first/second source node of the second pseudo-10T NVSRAM cell is the third/fourth flash source terminal;

wherein the first Charger transistor and the second Charger transistor are configured to generate coupling charges by ramping the second word line to the VDD level followed by ramping the pump word line to a level above the VDD level and to use a charge-sensing scheme and voltage-follower operation for performing a Recall operation to write a Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell to corresponding SRAM logic state stored by voltage levels of the first data node and the second data node in corresponding the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell.

22. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein each of the first Flash transistor and the second Flash transistor in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

23. The paired pseudo-10T NVSRAM memory cell of claim 22 wherein each of the first Charger transistor and the second Charger transistor is a same type as each of the first Flash transistor and the second Flash transistor no matter that is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

24. The paired pseudo-10 T NVSRAM memory cell of claim 23 wherein the SRAM cell in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell is subjected to a Read and Write operation by setting the first word line to the VDD level if the SRAM cell is selected or to VSS=0V if the SRAM cell is not selected and applying the VDD level to the first power line and VSS to the second power line, while setting the select-gate control line to VSS along with a Don'"'"'t care state for the second word line and the pump word line to isolated each SRAM cell from each corresponding Flash cell.

25. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein the Flash cell in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell is subjected to a an Erase operation including a preset step by setting both the first data node and the second data node to VSS under a condition of setting the first word line to the VDD level, the first power line to VSS, the second power line to VSS, the select-gate control line to VSS, followed by an erase step by applying a negative high voltage VNN to the second word line to decrease threshold levels of both the first Flash transistor and the second Flash transistor to ≦

−

2V under a FN-channel scheme in less than 5 ms, along with a Don'"'"'t care state for the pump word line.

26. The paired pseudo-10T NVSRAM memory cell of claim 25 wherein the negative high voltage VNN is about −

18V for a 2-poly floating-gate type flash transistor or about −

10V for a 1-poly charge-trapping type flash transistor, and the VDD level is about 1V to 2V.

27. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein the Flash cell in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

1”

of the SRAM cell with the first data node at the VDD level and the second data node at VSS=0V, the Program operation further including a programming step of applying the VDD level to the select-gate control line and ramping the second word line from VSS to a positive high voltage VPP to use a FN-channel scheme to maintain threshold level of the first Flash transistor and increase threshold level of the second Flash transistor to a positive value along with a Don'"'"'t care state for the pump word line, thereby storing the flash logic state “

0”

in the Flash cell.

28. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein the Flash cell in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell is subjected to a Program operation for defining a flash logic state, the Program operation including a preset step of setting the first word line to VSS, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

0”

of the SRAM cell with the first data node at VSS and the second data node at the VDD level, the Program operation further including a programming step of applying the VDD level to the select-gate control line and ramping the second word line from VSS to a positive high voltage VPP to use a FN-channel scheme to increase threshold level of the first Flash transistor to a positive value and maintain threshold level of the second Flash transistor along with a Don'"'"'t care state for the pump word line, thereby storing the flash logic state “

1”

in the Flash cell.

29. The paired pseudo-10T NVSRAM memory cell of claim 28 wherein the positive voltage VPP is about +18V for a 2-poly floating-gate type flash transistor or about +10V for a 1-poly charge-trapping type flash transistor.

30. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein the SRAM cell in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell is subjected to a Recall operation for writing a flash logic state stored in the Flash cell back to the first data node and the second data node under a charge-sensing scheme, the flash logic state including at least a state “

1”

defined by a Vt1 threshold level for the first Flash transistor and a Vt0<

0<

Vt0 threshold level for the second Flash transistor or a state “

0”

defined by a Vt0 threshold level for the first Flash transistor and a Vt1>

0>

Vt0 threshold level for the second Flash transistor.

31. The paired pseudo-10T NVSRAM memory cell of claim 30 wherein the Recall operation for writing a flash logic state “

1”

to the SRAM cell comprises initializing the SRAM cell with the first data node and the second data node, the first bit line and the second bit line, the first power line and the second power line all at VSS=0V by pulsing the first word line to the VDD level, and setting the second word line and the pump word line to VSS, followed by firstly ramping the second power line from VSS to the VDD level, secondly ramping the second word line from VSS to the VDD level, and thirdly ramping the pump word line from VSS to a voltage substantially above the VDD level, and sequentially ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step followed by ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step.

32. The paired pseudo-10T NVSRAM memory cell of claim 31 wherein the Recall operation further comprises setting the select-gate control line to the VDD level plus a threshold level of either the first Select transistor or the second Select transistor.

33. The paired pseudo-10T NVSRAM memory cell of claim 31 wherein firstly ramping the second power line from VSS to the VDD level comprises forming a reversed bias condition for the two Inverters of the SRAM cell to prevent charges in the first data node and the second data node from leaking.

34. The paired pseudo-10T NVSRAM memory cell of claim 31 wherein secondly ramping the second word line from VSS to the VDD level comprises detecting a coupling charge difference between the first Flash transistor and the second Flash transistor due to Vt0<

Vt1.

35. The paired pseudo-10T NVSRAM memory cell of claim 34 wherein thirdly ramping the pump word line from VSS to the voltage substantially above the VDD level comprises keeping gate voltage of the first Charger transistor and the second Charger transistor below a programming voltage VPP of +18V for generating coupling charges in drain nodes of the first Charger transistor and the second Charger transistor, the coupling charges being passed with the coupling charge difference using a voltage-follower operation through the first Flash transistor and the first Select transistor to the first data node with a first level of charges and respectively through the second Flash transistor and the second Select transistor to the second data node with a second level of charges, the first level being higher than the second level due to Vt0<

Vt1.

36. The paired pseudo-10T NVSRAM memory cell of claim 35 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step comprises pulling up the first level of charges at the first data node to substantially the VDD level and pulling up the second level of charges at the second data node to a third level of charges, the third level being lower than the VDD level.

37. The paired pseudo-10T NVSRAM memory cell of claim 36 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step comprises pulling down the third level of charges at the second data node to VSS=0V while maintaining the VDD level at the first data node.

38. The paired pseudo-10T NVSRAM memory cell of claim 36 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level in a first amplification step comprises coupling the second word line to a negative bias voltage to turn off both the first Flash transistor and the second Flash transistor.

39. The paired pseudo-10T NVSRAM memory cell of claim 37 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level in a second amplification step comprises coupling the second word line to a negative bias voltage below a lowest threshold level to turn off both the first Flash transistor and the second Flash transistor.

40. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein the Recall operation further comprises setting the first word line to the VDD level and resetting the first power line to the VDD level, the second power line to VSS, the select-gate control line to VSS, and the second word line to VSS=0V to return to a SRAM operation with a loaded logic state “

1”

associated with the VDD at the first data node and VSS at the second data node.

41. The paired pseudo-10T NVSRAM memory cell of claim 30 wherein the Vt0 is preferred to be a negative value about −

2V and the Vt1 is preferred to be a positive value above the VDD level.

42. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein the first Charger transistor and the second Charger transistor are configured to optionally have their channel lengths doubled for generating doubled charges shared with the first pseudo-10T NVSRAM cell and the second pseudo-10T NVSRM cell enough for performing the Recall operation under the charge-sensing scheme when the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the first pseudo-10 T NVSRAM cell is same as the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the second pseudo-10T NVSRAM cell.

43. The paired pseudo-10T NVSRAM memory cell of claim 21 wherein the first Charger transistor and the second Charger transistor are configured to have their original channel lengths for generating the charges separately for the first pseudo-10T NVSRAM cell and the second pseudo-10T NVSRM cell enough for performing the Recall operation under the charge-sensing scheme when the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the first pseudo-10T NVSRAM cell is opposite to the Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in the second pseudo-10T NVSRAM cell.