IP communication device and single-oscillator radio and oscillator control method

• US 8,976,777 B2
• Filed: 10/12/2010
• Issued: 03/10/2015
• Est. Priority Date: 10/15/2009
• Status: Active Grant

• Current Assignee: Sagemcom Energy & Telecom SAS (Sagemcom Holding SAS)
• Original Assignee: Sagemcom Energy & Telecom SAS (Sagemcom Holding SAS)
• Inventors: Jourdain, Laurent, Donnenwirth, Freddy, Geheniau, Frdric
• Primary Examiner(s): Phunkulh, Bob
• Assistant Examiner(s): CLARK, ROSENE S
• Application Number:
  US13/501,616
• Publication Number:
  US 20120201236A1
• Time in Patent Office: 1,610 Days
• Field of Search: 375354-360, 331 1- 25, 370/350, 370/503
• US Class Current: 370/350
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node

Abstract

The invention relates to the field of radio communication devices and, more specifically, gateways connected firstly to a cellular radio communication network via a packet data communication network, such as an IP network, and secondly to cellular mobile communication terminals. The invention proposes to use the same oscillator to provide both the reference clock of the radio subsystem and the reference clock of the general processor of the device. The fact that the same oscillator is used for these two components also allows embodiments in which some of the functions that have hitherto been devolved to a hardware control component, itself operating by means of a clock derived from the radio oscillator and being involved in the control of said oscillator, can now be devolved to a software component that is executed on the general processor of the gateway.

Claims

1. A communication device comprising:

a communication interface with a packet communication network;

a general processor;

a radio communication subsystem;

an oscillator for generating a reference clock signal of the radio communication subsystem;

wherein the communication device also comprises

a clock synthesizer for generating the reference clock of the general processor and the reference clock of the radio subsystem from the single oscillator,

wherein the communication device stores software intended to be executed by the general processor for synchronizing the reference clock signal of the radio communication subsystem with at least one distant reference source over the packet communication network by;

timestamping data packets exchanged between the device and the distant reference source;

controlling the frequency of the oscillator; and

implementing a time synchronization protocol that generates samples with two values, a first one relating to the stability of the clock and a second relating to the frequency drift, and an algorithm controlling the single oscillator for generating a voltage value from samples issuing from the time synchronization protocol.

2. The communication device according to claim 1, wherein the communication device stores software intended to be executed by the general processor for maintaining the oscillator at constant temperature by means of a radiator.

3. The communication device according to claim 1, wherein, the general processor having a Pulse Width Modulation converter, the oscillator control algorithm is intended to generate a Pulse Width Modulation signal by means of this converter from the voltage value;

the communication device further comprising a circuit that converts the Pulse Width Modulation signal into a voltage signal applied to the oscillator shaped and filtered with sufficient precision and stability to ensure the final precision of the frequency of the system.

4. The communication device according to claim 3, wherein said circuit is composed of:

a voltage calibrator receiving the Pulse Width Modulation signal;

a second-order low-pass filter filtering the output of the voltage calibrator; and

an operational amplifier connected as a follower and interposed between the output of the second-order low-pass filter and the oscillator.

5. The communication device according to claim 4, wherein a logic gate is interposed between the Pulse Width Modulation converter and the voltage calibrator and is adapted to reduce the transition times of the Pulse Width Modulation signal.

6. The communication device according to claim 1, wherein the oscillator control algorithm is intended to:

receive samples issued from the synchronization protocol;

eliminate the samples the stability of which is insufficient;

sort the qualified samples by the drift value thereof and eliminating the samples with the smallest and greatest drift;

calculate the average of the drift of the remaining samples; and

calculate the voltage value from the average.

7. A method of controlling an oscillator, the method being implemented in a communication device comprising said oscillator, a general processor and a radio communication subsystem, said oscillator generating a reference clock signal of the radio communication subsystem, the reference clock signal of the radio communication subsystem being synchronized with at least one distant reference source through a packet communication network,

wherein, the reference clock of the general processor and the reference clock of the radio subsystem being generated from a single oscillator, the method comprises, implemented in software form by the general processor:

generating, according to a time synchronization protocol, samples with two values, a first one relating to a clock stability and a second one relating to a frequency drift;

generating, according to an oscillator control algorithm, a voltage value from the samples issued from the time synchronization protocol generating said voltage value comprising;

receiving the samples issued from the time synchronization protocol;

eliminating the samples the stability of which is insufficient;

sorting the qualified samples by the drift value thereof and eliminating the samples with the smallest and greatest drift;

calculating the average of the drift of the remaining samples; and

calculating the voltage value from the average.