Power supply filtering for programmable logic device having heterogeneous serial interface architecture

• US 8,976,804 B1
• Filed: 03/07/2011
• Issued: 03/10/2015
• Est. Priority Date: 04/11/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Shumarayev, Sergey, Wong, Wilson, Tran, Thungoc M., Hoang, Tim Tri
• Primary Examiner(s): NGUYEN, STEVEN H D
• Application Number:
  US13/041,764
• Time in Patent Office: 1,464 Days
• Field of Search: None
• US Class Current: 370/419
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

Claims

1. Filter circuitry for an integrated circuit, said integrated circuit fabricated on a die which is packaged in a package, said filter circuitry comprising

die-level filtering circuitry for filtering out noise in a first range of frequencies;

and

package-level filtering circuitry for filtering out noise in a second range of frequencies lower than said first range of frequencies,

wherein the first range of frequencies and the second range of frequencies is disjoint, wherein the die-level filter circuitry comprises a filter network and a selectable bypass for the filter network.

2. The filter circuitry of claim 1 wherein at least one of said die-level filtering circuitry and said package-level filtering circuitry has a reactance.

3. The filter circuitry of claim 1 wherein said package-level filtering circuitry comprises selective routing of power relative to ground.

4. The filter circuitry of claim 1 wherein said die-level filtering circuitry comprises one of (a) a filter network, and (b) a regulator circuit, each of said filter network and said regulator circuit being matched to a respective portion of said integrated circuit.

5. The filter circuitry of claim 4 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each of said respective filter network and said respective regulator.

6. The filter circuitry of claim 1 wherein, when said package is mounted on a circuit board, said filter circuitry further comprises at least one of:

said die-level filtering circuitry;

said package-level filtering circuitry; and

board-level filtering circuitry for filtering a third range of frequencies lower than said second range of frequencies.

7. The filter circuitry of claim 1 wherein:

said integrated circuit comprises at least one of a voltage-controlled oscillator, a loop filter, and a charge pump; and

said filter circuitry further comprises said die-level filter circuitry to filter said at least one of said voltage-controlled oscillator, said loop filter, and said charge pump.

8. The filter circuitry of claim 7 wherein said die-level filter circuitry comprises one of (a) a filter network, and (b) a regulator circuit, each of said filter network and said regulator circuit being matched to said at least one of said voltage-controlled oscillator, said loop filter, and said charge pump.

9. The filter circuitry of claim 8 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each of said filter network and said regulator.

10. The filter circuitry of claim 9 wherein said die-level filter circuitry further has a reactance.

11. A system comprising:

a circuit board;

a package mounted on said circuit board;

a die packaged in said package;

an integrated circuit fabricated on said die;

functional circuitry mounted on said circuit board and functionally coupled to said integrated circuit;

wherein;

said system includes filter circuitry operable to filter signals on at least one of said integrated circuit and said functional circuitry, and comprising die-level filtering circuitry for filtering out noise in a first range of frequencies;

package-level filtering circuitry for filtering out noise in a second range of frequencies lower than said first range of frequencies; and

board-level filtering circuitry for filtering out noise in a third range of frequencies lower than said second range of frequencies, wherein the first range of frequencies and the second range of frequencies is disjoint, wherein the die-level filter circuitry comprises a filter network and a selectable bypass for the filter network.

12. The system of claim 11 wherein at least one of said die-level filtering circuitry, said package-level filtering circuitry, and said board-level filtering circuitry, has a reactance.

13. The system of claim 11 wherein said package-level filtering circuitry comprises selective routing of power relative to ground.

14. The system of claim 11 wherein said die-level filtering circuitry comprises one of (a) a filter network, and (b) a regulator circuit, each of said filter network and said regulator being matched to a respective portion of said integrated circuit.

15. The system of claim 14 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each of said filter network and said regulator.

16. A device comprising:

a circuit board;

a package mounted on said circuit board;

a die packaged in said package; and

an integrated circuit fabricated on said die;

wherein;

said integrated circuit comprises first circuitry operating at a first data rate, second circuitry operating at a second data rate higher than said first data rate, and third circuitry operating at a third data rate higher than said second data rate; and

said device further comprises filter circuitry including;

die-level filtering circuitry for filtering out noise in signals on said third circuitry;

package-level filtering circuitry for filtering out noise in signals on said second circuitry; and

board-level filtering circuitry for filtering out noise in signals on said first circuitry, wherein the die-level filtering circuitry and the package-level filtering circuitry filter out noise in disjoint frequency ranges, wherein the die-level filter circuitry comprises a filter network and a selectable bypass for the filter network.

17. The device of claim 16 wherein at least one of said die-level filtering circuitry, said package-level filtering circuitry, and said board-level filtering circuitry, has a reactance.

18. The device of claim 16 wherein said package-level filtering circuitry comprises selective routing of power relative to ground.

19. The device of claim 16 wherein said die-level filtering circuitry comprises one of (a) a filter network, and (b) a regulator circuit, each of said filter network and said regulator circuit being matched to a respective portion of said integrated circuit.

20. The device of claim 19 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each of said filter network and said regulator.