Method of improving peripheral component interface communications utilizing a low voltage differential signal channel

• US 8,977,797 B2
• Filed: 10/10/2012
• Issued: 03/10/2015
• Est. Priority Date: 05/14/1999
• Status: Expired due to Fees

• Current Assignee: Acqis LLC (Acqis Technology, Inc.)
• Original Assignee: Acqis LLC (Acqis Technology, Inc.)
• Inventors: Chu, William W. Y.
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US13/649,084
• Publication Number:
  US 20130097352A1
• Time in Patent Office: 881 Days
• Field of Search: 710300-304, 710313-315, 710 62- 64, 710 72- 74, 709214- 21, 709226-227, 726 2- 9, 726 16- 21, 726/34, 726/36, 713182-183, 713192-194
• US Class Current: 710/313
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Claims

1. A method of improving computer peripheral data communications, comprising:

connecting a Central Processing Unit (CPU) directly to a peripheral bridge on a printed circuit board of a computer system;

connecting a Low Voltage Differential Signal (LVDS) channel directly to the peripheral bridge on the printed circuit board, the LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form over the serial channels to preserve the PCI bus transaction;

coupling the peripheral bridge to an Ethernet connection through the LVDS channel to improve data throughput between the CPU and the Ethernet connection;

using the Ethernet connection to connect the computer system to an Ethernet network; and

applying power to the computer system.

2. The method of claim 1 further comprising attaching system memory directly to the CPU.

3. The method of claim 1 further comprising:

coupling a mass storage device to the CPU; and

using flash memory as a mass storage device.

4. A method of improving computer peripheral data communications, comprising:

mounting a Central Processing Unit (CPU) on a printed circuit board of a computer system;

connecting a Low Voltage Differential Signal (LVDS) channel directly to the CPU on the printed circuit board, the LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form over the serial channels to preserve the PCI bus transaction;

coupling the CPU to a peripheral device through the LVDS channel; and

applying power to the computer system.

5. The method of claim 4 further comprising attaching system memory directly to the CPU.

6. The method of claim 4 further comprising:

coupling a mass storage device to the CPU; and

using flash memory as a mass storage device.

7. A method of improving computer storage data throughput, comprising:

connecting a Central Processing Unit (CPU) directly to a peripheral bridge on a printed circuit board of a computer system,

connecting a Low Voltage Differential Signal (LVDS) channel directly to the peripheral bridge on the printed circuit board, the LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form over the serial channels to preserve the PCI bus transaction;

coupling the peripheral bridge to a mass storage device through the LVDS channel; and

applying power to the computer system.

8. The method of claim 7 further comprising attaching system memory directly to the CPU.

9. The method of claim 7 further comprising using flash memory for mass storage.

10. A method of improving peripheral data performance on a motherboard, comprising:

connecting a Central Processing Unit (CPU) directly to a peripheral bridge on a motherboard,

connecting a Low Voltage Differential Signal (LVDS) channel directly to the peripheral bridge on the motherboard, the LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form over the serial channels to preserve the PCI bus transaction;

attaching an Ethernet connector to the motherboard for connection to an Ethernet network; and

coupling the peripheral bridge to the Ethernet connector through the LVDS channel.

11. The method of claim 10 further comprising using the motherboard and the LVDS channels in a computer system.

12. The method of claim 10 further comprising:

providing sockets for memory modules on the motherboard that connect directed to the CPU; and

populating the sockets with system memory.

13. The method of claim 10 further comprising:

providing a connector on the motherboard for adding a mass storage device; and

utilizing flash memory for the mass storage device.

14. A method of improving data throughput on a motherboard, comprising:

mounting a Central Processing Unit (CPU) on a motherboard;

connecting a Low Voltage Differential Signal (LVDS) channel directly to the CPU on the motherboard, the LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form over the serial channels to preserve the PCI bus transaction; and

coupling the CPU to a peripheral device attached to the motherboard through the LVDS channel.

15. The method of claim 14 further comprising:

having the peripheral device support Ethernet communication; and

using the motherboard in a computer system to improve Ethernet network data throughput to the CPU.

16. The method of claim 14 further comprising:

providing sockets for memory modules on the motherboard that connect directly to the CPU; and

populating the sockets with system memory to improve system performance.

17. The method of claim 14 further comprising:

mounting a connector on the motherboard for a mass storage device; and

utilizing flash memory for the mass storage device.

18. A method of increasing external peripheral data communication speed of a computer, comprising:

connecting a Central Processing Unit (CPU) directly to a peripheral bridge on a printed circuit board of a computer system;

connecting a first Low Voltage Differential Signal (LVDS) channel directly to the peripheral bridge on the printed circuit board, the first LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

providing a connector for the computer system that can connect to a console;

providing a second LVDS channel to couple to the console through the connector, the second LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form over the first and second LVDS channels to preserve the PCI bus transaction; and

conveying the encoded PCI bus transaction serially through the second LVDS channel to the console.

19. The method of claim 18 further comprising attaching system memory directly to the CPU.

20. The method of claim 18 further comprising providing digital video signals through the same connector to an external display.

21. A method of increasing external peripheral data communication speed of a computer, comprising:

providing an integrated Central Processing Unit (CPU) and graphics controller in a single chip, on a printed circuit board of a computer system;

providing digital video signals directly from the integrated Central Processing Unit (CPU) and graphics controller;

connecting a first Low Voltage Differential Signal (LVDS) channel directly to a peripheral bridge on the printed circuit board, the first LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

providing a connector for the computer system that can connect to a console;

providing a second LVDS channel to couple to the console through the connector, the second LVDS channel comprising two unidirectional, serial channels that transmit data in opposite directions;

conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form over the second LVDS channel to preserve the PCI bus transaction; and

conveying the encoded PCI bus transaction serially through the second LVDS channel to the console.

22. The method of claim 21 further comprising attaching system memory directly to the CPU.

23. The method of claim 21 further comprising coupling the digital video signals from the integrated CPU and graphics controller through the connector to an external display.

24. A method of improving data communication within a modular server, comprising:

coupling a first integrated CPU and graphics controller chip to a first printed circuit board;

coupling a first Low Voltage Differential Signal (LVDS) channel to the first integrated CPU and graphics controller chip, wherein the first LVDS channel comprises two unidirectional, serial channels to transmit an encoded Peripheral Component Interconnect (PCI) bus transaction in serial form in opposite directions;

coupling the first LVDS channel directly to a first connector;

coupling a second integrated CPU and graphics controller chip to a second printed circuit board;

coupling a second LVDS channel to the second integrated CPU and graphics controller chip, wherein the second LVDS channel comprises two unidirectional, serial channels to transmit an encoded Peripheral Component Interconnect (PCI) bus transaction in serial form in opposite directions;

coupling the second LVDS channel directly to a second connector;

coupling the first and second connectors to a third printed circuit board;

coupling a hub controller to the third printed circuit board; and

coupling the first and second LVDS channels directly to the hub controller with point to point connections for each channel through the third printed circuit board to communicate using a PCI protocol.

25. The method of claim 24 further comprising

coupling a mass storage device to the first integrated CPU and graphics controller chip, wherein the mass storage device resides on the first printed circuit board.

26. The method of claim 25 wherein the mass storage device comprises flash memory.

27. A method of improving data communication within a computer, comprising:

connecting an integrated Central Processing Unit (CPU) and graphics controller chip to a printed circuit board within the computer,

connecting a first Low Voltage Differential Signal (LVDS) channel directly to the integrated CPU and graphics controller chip, wherein the first LVDS channel comprises two unidirectional, serial channels that transmit data in opposite directions;

connecting a second LVDS channel directly to a connector, comprising two unidirectional, serial channels that transmit data in opposite directions;

conveying Universal Serial Bus (USB) protocol data over the first LVDS channel; and

coupling the first LVDS channel to the connector through the second LVDS channel.

28. The method of claim 27 further comprising

coupling a cable to the connector for communicating USB protocol data to a console, wherein the console comprises a power supply.

29. The method of claim 28 further comprising:

supplying power to the computer from the console upon coupling.

30. A method of improving peripheral data communication within a computer, comprising:

connecting an integrated Central Processing Unit (CPU) and graphics controller chip directly to a first Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, serial channels that transmit data in opposite directions;

conveying Universal Serial Bus (USB) protocol data over the first LVDS channel;

coupling a second LVDS channel directly to the integrated CPU and graphics controller;

conveying digital video signals through the second LVDS channel;

coupling the first LVDS channel to a connector to communicate using a USB protocol.

31. The method of claim 30 further comprising

coupling the connector to a console through a cable to communicate using a USB protocol.

32. The method of claim 30 further comprising

conveying Transition Minimized Differential Signaling (TDMS) signals over the second differential signal channel.

33. A method of improving external peripheral data performance within a computer, comprising:

coupling an integrated Central Processing Unit (CPU) and graphics controller chip to a connector,

conveying a first Low Voltage Differential Signal (LVDS) channel through the connector comprising two unidirectional, serial channels that transmit data in opposite directions;

conveying Universal Serial Bus (USB) protocol data from the integrated CPU and graphics controller chip, over the first LVDS channel for external USB protocol data communication.

34. The method of claim 33 further comprising

connecting a second differential signal channel directly to the integrated CPU and graphics controller chip to output digital video signals.

35. The method of claim 34 further comprising:

conveying Transition Minimized Differential Signaling (TDMS) signals over the second differential signal channel.

36. A method of improving data throughput on a motherboard, comprising:

mounting an integrated Central Processing Unit (CPU) and interface controller as a single chip on a motherboard;

connecting a Low Voltage Differential Signal (LVDS) channel directly to the interface controller on the motherboard, wherein the LVDS channel comprises two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple differential signal line pairs;

configuring the interface controller to adapt to different numbers of differential signal line pairs for conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form; and

coupling the integrated CPU and interface device to a peripheral device attached to the motherboard through the LVDS channel with the adapted number of differential signal line pairs.

37. The method of claim 36 further comprising:

having the peripheral device support Ethernet communication; and

using the motherboard in a computer system to improve Ethernet network data throughput to the integrated CPU and interface controller.

38. The method of claim 36 further comprising:

providing Phase-Locked Loop (PLL) clock circuitry in the single chip coupled to the interface controller; and

configuring the interface controller to generate different data transfer frequencies to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.