Hybrid memory module

• US 8,977,806 B1
• Filed: 09/15/2012
• Issued: 03/10/2015
• Est. Priority Date: 10/05/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rosenband, Daniel L., Weber, Frederick Daniel, Smith, Michael John Sebastian
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US13/620,793
• Time in Patent Office: 906 Days
• Field of Search: 711/102, 711/103, 711/104, 711/105, 711/111, 711/148, 711/154
• US Class Current: 711/103
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 off-chip wires

Abstract

One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.

Claims

1. A memory module, comprising:

a plurality of sub-stacks including memory devices of a first type, each sub-stack comprising;

a respective plurality of memory devices of the first type; and

a respective sub-controller configured to control the respective plurality of memory devices of the first type;

a super-controller configured to control each of the sub-controllers of the plurality of sub-stacks; and

a host interface coupled to the super-controller and configured to transmit data to a memory controller.

2. The memory module of claim 1, further comprising a super-stack interface configured to transmit data between the super-controller and the host interface.

3. The memory module of claim 1, wherein each sub-stack further includes a respective interface configured to communicate data between the sub-controller and the super-controller.

4. The memory module of claim 3, wherein each sub-controller further comprises command queuing logic configured to:

receive first data from the plurality of memory devices;

multiplex the first data to produce multiplexed data; and

transmit the multiplexed data to the super-controller via the interface.

5. The memory module of claim 3, wherein each sub-controller further comprises high-speed interface logic configured to convert data of a first signaling speed to data of a second signaling speed.

6. The memory module of claim 1, wherein the super-controller includes protocol logic configured to convert a first protocol to a second, different protocol.

7. The memory module of claim 1,

wherein the super-controller is configured to:

communicate with a memory controller using a first memory channel protocol having a first signaling speed; and

communicate with the sub-controllers using a second memory channel protocol having a second signaling speed, the second signaling speed being different from the first signaling speed,

wherein the super-controller further comprises a signaling translation unit configured to translate data, clock, command, and control signals from the first memory channel protocol having the first signaling speed to the second memory channel protocol having the second signaling speed.

8. The memory module of claim 1, wherein the super-controller further comprises interleave logic configured to multiplex or demultiplex data between the sub-stacks and the host interface.

9. The memory module of claim 1, wherein each sub-controller further comprises:

a respective fast memory device;

a respective flash controller configured to provide interface, mapping, error detection, or error correction functionality to the respective plurality of memory devices; and

a respective flash interface configured to transmit data between the flash controller and the plurality of memory devices.

10. The memory module of claim 9, wherein the fast memory device comprises a volatile memory device, and wherein the plurality of memory devices comprise non-volatile memory devices.

11. The memory module of claim 9, wherein the fast memory device comprises a volatile memory device of a first signaling speed, and wherein the plurality of memory devices comprise volatile memory devices of a second, different signaling speed.

12. The memory module of claim 9, wherein the fast memory device is configured to hold data stored at one or more of the respective plurality of memory devices.

13. The memory module of claim 1, wherein the respective plurality of memory devices of a particular sub-stack are vertically stacked using through-silicon vias.

14. The memory module of claim 1, wherein the respective plurality of memory devices of a particular sub-stack are vertically stacked using wire-bonded connections.

15. The memory module of claim 1, wherein the plurality of sub-stacks are stacked vertically to form a super stack.

16. The memory module of claim 15, wherein the plurality of sub-stacks are stacked vertically on the super-stack controller.

17. A memory module, comprising:

a first sub-stack comprising;

first memory devices of a particular type; and

a first sub-controller configured to control the first memory devices of the particular type;

a second sub-stack comprising;

second memory devices of the particular type; and

a second sub-controller configured to control the second memory devices of the particular type;

a super-controller configured to control the first sub-controller of the first sub-stack and the second sub-controller of the second sub-stack; and

a host interface coupled to the super-controller and configured to transmit data to a memory controller.

18. The memory module of claim 17, wherein the first sub-controller is stacked on a first area of the super-controller, and wherein the second sub-controller is stacked on a second area of the super-controller.

19. The memory module of claim 18, wherein the first sub-stack is stacked on the super-controller, and the second sub-stack is stacked on the first sub-stack.

20. An apparatus, comprising:

a multi-chip package (MCP) substrate;

a memory controller situated on a first area of the MCP substrate;

a plurality of sub-stacks including memory devices of a first type, each sub-stack comprising;

a respective plurality of memory devices of the first type; and

a respective sub-controller configured to control the respective plurality of memory devices of the first type;

a super-controller situated on a second area of the MCP substrate and configured to control each of the sub-controllers of the plurality of sub-stacks; and

a host interface coupled to the super-controller and configured to transmit data to the memory controller.