Implementing RAID in solid state memory

• US 8,977,813 B2
• Filed: 04/23/2014
• Issued: 03/10/2015
• Est. Priority Date: 09/15/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Burd, Gregory
• Primary Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US14/260,237
• Publication Number:
  US 20140237287A1
• Time in Patent Office: 321 Days
• Field of Search: 711/114, 711/5, 711/103, 711/154, 711/156, 714/6.11, 714/6.22, 714/6.24, 714/6.32, 365/185.33
• US Class Current: 711/114
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1028 Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data request for a solid state memory; identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory; reading stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and recovering data of at least one block of the logical block grouping based on the stored data and the parity information.

Claims

1. A method comprising:

receiving, at a storage controller, a data request for a solid state memory;

identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory;

reading, by the storage controller, stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and

recovering data of at least one block of the logical block grouping based on the stored data and the parity information.

2. The method of claim 1, wherein the at least two distinct memory units are device planes, and each of the device planes comprises individually addressable physical data storage blocks.

3. The method of claim 2, wherein the solid state memory comprises at least two solid state memory devices, and the identifying comprises identifying the device planes, which span the at least two solid state memory devices.

4. The method of claim 3, wherein each of the physical data storage blocks of the logical block grouping is in a different one of the at least two solid state memory devices.

5. The method of claim 1, wherein the at least two distinct memory units are solid state memory devices including at least one dedicated parity device.

6. The method of claim 1, wherein a physical data storage block is a smallest erasable unit in the solid state memory.

7. The method of claim 1, wherein the identifying is an emulated function performed in accordance with a user selected RAIB (Redundant Array of Independent Blocks) coderate.

8. The method of claim 1, comprising interleaving pages across different RAIB associations using different parity buffers.

9. The method of claim 1, wherein a RAIB stripe coincides with a logical block grouping used for wear leveling in the solid state memory.

10. A solid state memory system comprising:

distinct memory units; and

a controller configured to identify a logical block grouping corresponding to a data request, wherein the logical block grouping indicates physical data storage blocks spanning the distinct memory units, and the controller configured to recover data of at least one block of the logical block grouping based on user data and parity information read from at least a portion of the physical data storage blocks spanning the distinct memory units.

11. The solid state memory system of claim 10, wherein the distinct memory units are device planes, and each of the device planes comprises individually addressable physical data storage blocks.

12. The solid state memory system of claim 11, comprising at least two solid state memory devices, wherein the device planes span the at least two solid state memory devices.

13. The solid state memory system of claim 12, wherein each of the physical data storage blocks of the logical block grouping is in a different one of the at least two solid state memory devices.

14. The solid state memory system of claim 10, wherein a physical data storage block is a smallest erasable unit in the solid state memory system.

15. The solid state memory system of claim 10, wherein the controller comprises:

a processor;

a buffer; and

an error correcting code (ECC) module.

16. The solid state memory system of claim 15, wherein the processor is programmed to identify the logical block grouping in accordance with a user selected RAIB (Redundant Array of Independent Blocks) coderate.

17. The solid state memory system of claim 15, comprising more than one parity buffer.

18. The solid state memory system of claim 17, wherein the processor is programmed to interleave pages across RAIB associations using the more than one parity buffer.

19. The solid state memory system of claim 17, wherein each of the more than one parity buffer comprises a single port memory.

20. The solid state memory system of claim 15, wherein a RAIB stripe coincides with a logical block grouping used for wear leveling in the solid state memory system.