Flash backed DRAM module storing parameter information of the DRAM module in the flash

• US 8,977,831 B2
• Filed: 02/11/2009
• Issued: 03/10/2015
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: Moshayedi, Mark, Finke, Douglas
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US12/369,046
• Publication Number:
  US 20100205348A1
• Time in Patent Office: 2,218 Days
• Field of Search: 711/103, 711/165, 714/22
• US Class Current: 711/165
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information.

Claims

1. A memory device comprising:

a plurality of volatile memory devices;

non-volatile memory system including a non-volatile memory device comprising a plurality of storage devices, the non-volatile memory system configured to store in the non-volatile memory device parameters describing one of the plurality of volatile memory devices;

an interface for connecting to a backup power source arranged to temporarily power the one of the plurality of volatile memory devices upon a loss of power from a primary power source; and

a controller in communication with the one of the plurality of volatile memory devices and the non-volatile memory, wherein the controller is programmed to move data from the one of the plurality of volatile memory devices to the same non-volatile memory device that is configured to store the non-volatile memory device parameters, upon a loss of power of the primary power source at the one of the plurality of the volatile memory devices, and cause the remaining volatile memory devices to enter into a low power mode;

wherein the controller is configured to store the data to the plurality of storage devices by splitting a data stream, which comprises the data, into a plurality of data streams.

2. The memory device of claim 1, wherein the parameters describing the one of the plurality of volatile memory devices comprise serial presence detect information, a size of the one of the plurality of volatile memory devices, or a speed of the one of the plurality of volatile memory devices.

3. The memory device of claim 1, wherein the controller further comprises a cache for storing the parameters.

4. The memory device of claim 1, further comprising a configuration data bus for accessing the parameters.

5. The memory device of claim 1, further comprising a configuration data bus for accessing the parameters, wherein the controller further comprises a cache for storing the parameters, and wherein the controller is further programmed to read the parameters from the cache in response to receiving a request for the parameters over the configuration data bus.

6. The memory device of claim 1, wherein the one of the plurality of volatile memory devices comprises a dynamic random access memory.

7. The memory device of claim 1, wherein the non-volatile memory device comprises electrically erasable programmable read-only memory.

8. The memory device of claim 1, wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

9. The memory device of claim 1, wherein the controller is further programmed to move data from the non-volatile memory device to the one of the plurality of volatile memory devices upon a restoration of power of the primary power source.

10. The memory device of claim 1, wherein power from the backup power source is primarily from a capacitor.

11. The memory device of claim 1, wherein power from the backup power source is primarily from a capacitor.

12. The memory device of claim 11, wherein the controller is configured to estimate a health of the capacitor by measuring an amount of time it takes to fully charge the capacitor.

13. The memory device of claim 1, wherein the data moved by the controller comprises directory information for determining a location of information.

14. The memory device of claim 1, wherein when the power of the primary power source returns before the controller finishes moving the data to the non-volatile memory device, the controller is further configured to enable retrieval of the data from the one of the plurality of volatile memory devices.

15. The memory device of claim 1, wherein, upon a loss of power of the primary power source for the plurality of volatile memory devices, the controller is programmed to move data from each of the plurality of volatile memory devices to the same non-volatile memory device in a sequential manner.

16. A method, comprising:

upon a loss of power of a primary power source at one of a plurality of volatile memory devices;

causing other volatile memory devices to enter into a low power mode; and

moving data from the one of the volatile memory devices to a non-volatile memory system, including a non-volatile memory device comprising a plurality of storage devices, based on parameters describing the one of the volatile memory devices, while the one of the volatile memory devices is temporarily powered by a backup power source, wherein the non-volatile memory device is configured to store both the data moved from the one of the volatile memory devices and the parameters describing the one of the volatile memory;

wherein moving the data comprises storing the data to the plurality of storage devices by splitting a data stream, which comprises the data, into a plurality of data streams.

17. The method of claim 16, wherein the parameters comprise serial presence detect information, a size of the one of the volatile memory devices, or a speed of the one of the volatile memory devices.

18. The method of claim 16, further comprising moving data from the non-volatile memory device to the one of the volatile memory devices upon a restoration of power of the primary power source.

19. The method of claim 16, wherein power from the backup power source is primarily from a capacitor.