Methods, systems, and articles of manufacture for dynamic protection of intellectual property in electronic circuit designs

• US 8,977,863 B1
• Filed: 08/30/2010
• Issued: 03/10/2015
• Est. Priority Date: 08/30/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Arsintescu, Bogdan
• Primary Examiner(s): Le, David
• Application Number:
  US12/871,756
• Time in Patent Office: 1,653 Days
• Field of Search: None
• US Class Current: 713/189
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Various embodiments describe methods and systems for dynamic IP protection in electronic circuit designs. The methods or systems determine one or more levels of access or encryption and identify design data that should be made available for each level. For each level, a pcell instance is created to hide actual design data, and the design data that should be made available are moved to an instance of the corresponding sub-master in memory. The design data in this instance are encrypted in memory and are persisted in a side file in a non-volatile computer accessible storage medium. An authorized user is provided with a key, the side file, and a decrypting scheme to retrieve the actual design data with an appropriate level of details from the side file during a pcell evaluation process.

Claims

1. A computer implemented method for implementing dynamic protection of intellectual property in an electronic circuit design, comprising:

using a computer system that comprises at least one processor or process core executing one or more threads to perform a process, the process comprising;

initiating an encapsulation process for a block of electronic design;

creating a first parameterized cell instance for the block of electronic design with a first level of encryption of or access to the block of electronic design, wherein the first parameterized cell includes some design data about the block but does not by itself contain or obtain design data that are needed to construct details of the first parameterized cell instance of the block within a boundary of the block of electronic design by a parameterized cell evaluation module in an electronic circuit design tool; and

encrypting a first set of design data associated with the first level of encryption or access in a first sub-master for the first parameterized cell instance with the first level of encryption or access.

2. The computer implemented method of claim 1, further comprising:

identifying or determining the design data that should be made available for the first level of encryption or access.

3. The computer implemented method of claim 1, wherein the action of creating the first parameterized cell instance and the act of encrypting the design data do not occur in a non-volatile computer accessible storage medium.

4. The computer implemented method of claim 1, further comprising:

creating a second parameterized cell instance for a second level of encryption or access.

5. The computer implemented method of claim 4, further comprising:

encrypting a second set of design data associated with the second level of encryption or access in a second sub-master for the second level of encryption or access.

6. The computer implemented method of claim 5, further comprising:

storing the second set of design data that is encrypted in a side file in the non-volatile computer accessible storage medium.

7. The computer implemented method of claim 1, further comprising:

providing a key to a user to unlock a side file, wherein the design data are decrypted from the side file using the key.

8. The computer implemented method of claim 7, further comprising:

providing a side file and a decryption scheme to the user.

9. The computer implemented method of claim 1, wherein the first parameterized cell instance does not comprise design data that are used to rebuild a part of the electronic circuit design.

10. The computer implemented method of claim 1, further comprising:

moving the design data into the first sub-master in a volatile computer accessible storage medium.

11. The computer implemented method of claim 9, wherein the first parameterized cell instance comprises a parameter for the first level of encryption or access and understands a scheme that is used for the act of encrypting the first set of design data.

12. An article of manufacture comprising a non-transitory computer accessible storage medium having a sequence of instructions which, when executed by at least one processor or processor core executing one or more threads, causes the at least one processor or processor core to perform a method for implementing dynamic protection of intellectual property in an electronic circuit design, comprising:

a program code which, when executed by at the least one processor of a computer system, causes the at least one processor to perform one or more acts, the one or more acts comprising;

initiating an encapsulation process for a block of electronic design;

creating a first parameterized cell instance for the block of electronic design with a first level of encryption of or access to the block of electronic design, wherein the first parameterized cell includes some design data about the block but does not by itself contain or obtain design data that are needed to construct details of the first parameterized cell instance of the block within a boundary of the block of electronic design by a parameterized cell evaluation module in an electronic circuit design tool; and

encrypting design data associated with the first level of encryption or access in a sub-master for the first parameterized cell instance with the first level of encryption or access.

13. The article of manufacture of claim 12, further comprising:

the program code which, when executed by the at least one processor, causes the at least one processor to perform an act of creating a second parameterized cell instance for a second level of encryption or access.

14. The article of manufacture of claim 13, further comprising:

the program code which, when executed by the at least one processor, causes the at least one processor to perform an act of encrypting a second set of design data associated with the second level of encryption or access in a second sub-master for the second level of encryption or access.

15. The article of manufacture of claim 14, the process further comprising:

the program code which, when executed by the at least one processor, causes the at least one processor to perform an act of storing the second set of design data that is encrypted in a side file in the non-volatile computer accessible storage medium.

16. The article of manufacture of claim 12, wherein the first parameterized cell instance does not comprise the enough design data that are used to rebuild a part of the electronic circuit design.

17. A system for implementing dynamic protection of intellectual property in an electronic circuit design, comprising:

a computer system that comprises at least one processor or processor core executing one or more threads and is at least to;

initiate an encapsulation process for a block of electronic design;

create a first parameterized cell instance for the block of electronic design with a first level of encryption of or access to the block of electronic design, wherein the first parameterized cell includes some design data about the block but does not by itself contain or obtain design data that are needed to construct details of the first parameterized cell instance of the block within a boundary of the block of electronic design by a parameterized cell evaluation module in an electronic circuit design tool; and

encrypt design data associated with the first level of encryption or access in a sub-master for the first parameterized cell instance with the first level of encryption or access.

18. The system of claim 17, the computer system is further to:

create a second parameterized cell instance for a second level of encryption or access.

19. The system of claim 18, the computer system is further to:

encrypt a second set of design data associated with the second level of encryption or access in a second sub-master for the second level of encryption or access.

20. The system of claim 19, the computer system is further to:

store the second set of design data that is encrypted in a side file in the non-volatile computer accessible storage medium.

21. The system of claim 17, wherein the first parameterized cell instance does not comprise design data that are used to rebuild a part of the electronic circuit design.

22. A computer implemented method for using a dynamically protected intellectual property block design in an electronic circuit design, comprising:

using a computer system that comprises at least one processor or process core executing one or more threads and is to perform a process, the process comprising;

identifying a side file for the dynamically protected intellectual property (IP) block design;

using a key to retrieve a sub-master of a plurality of sub-masters of the dynamically protected IP block design, wherein the sub-master includes some design data about the dynamically protected block but does not by itself contain or obtain design data that are needed to construct details of an instance of the dynamically protected IP block within a boundary of the dynamically protected IP block by a parameterized cell evaluation module in an electronic circuit design tool; and

instantiating the instance of the dynamically protected IP block design in the electronic circuit design by using an instance of the sub-master.

23. The computer implemented method of claim 22, in which the side file comprises the plurality of sub-masters of the IP block design, each of which corresponds to an encryption or access level of a plurality of encryption or access levels.

24. The computer implemented method of claim 22, in which the instance of the one of the sub-masters is used to protect actual data of the IP block design.

25. The computer implemented method of claim 24, in which the instance of the one of the sub-masters does not comprise the actual data other than boundary information of the IP block design.

26. The computer implemented method of claim 22, further comprising:

preventing an access to another one of the plurality of sub-masters of the IP block design with the key.

27. The computer implemented method of claim 22, in which the act of using the key to retrieve one of the plurality of sub-masters of the IP block design comprises:

identifying at least a portion of the side file, in which the portion is associated with the key; and

performing a decryption process on the portion to retrieve the one of the plurality of sub-masters of the IP block design.

28. The computer implemented method of claim 22, further comprising:

identifying a reference from the side file to a second side file, in which the second side file comprises a second actual design data for a second IP block design;

using a second key to retrieve one of a second plurality of sub-masters of the second IP block design; and

instantiating the second IP block design in the electronic circuit design by using a second instance of the one of the second plurality of sub-masters.

29. A system for using a dynamically protected intellectual property block design in an electronic circuit design, comprising:

a computer system that comprises at least one processor or process core executing one or more threads and is to;

identify a side file for the dynamically protected intellectual property (IP) block design;

use a key to retrieve a sub-master of a plurality of sub-masters of the dynamically protected IP block design, wherein the sub-master includes some design data about the dynamically protected block but does not by itself contain or obtain design data that are needed to construct details of an instance of the dynamically protected IP block within a boundary of the dynamically protected IP block by a parameterized cell evaluation module in an electronic circuit design tool; and

initiate an instance the dynamically protected IP block design in the electronic circuit design by using an instance of the sub-master.

31. The system of claim 29, in which the computer system is further to:

prevent an access to another one of the plurality of sub-masters of the IP block design with the key.

32. The system of claim 29, in which the computer system that is to use the key to retrieve one of the plurality of sub-masters of the IP block design is further to:

identify at least a portion of the side file, in which the portion is associated with the key; and

perform a decryption process on the portion to retrieve the one of the plurality of sub-masters of the IP block design.

33. The system of claim 29, in which the computer system is further to

identify a reference from the side file to a second side file, in which the second side file comprises a second actual design data for a second IP block design;

use a second key to retrieve one of a second plurality of sub-masters of the second IP block design; and

instantiate the second IP block design in the electronic circuit design by using a second instance of the one of the second plurality of sub-masters.

30. An article of manufacture comprising a non-transitory computer accessible storage medium having a sequence of instructions which, when executed by at least one processor or processor core executing one or more threads, causes the at least one processor or processor core to perform a method for using a dynamically protected intellectual property block design in an electronic circuit design, the method comprising:

a program code which, when executed by at least one processor or processor core executing one or more threads of a computer system, causes the at least one processor to perform one or more acts, the one or more acts comprising;

identifying a side file for the dynamically protected intellectual property (IP) block design;

using a key to retrieve a sub-master of a plurality of sub-masters of the dynamically protected IP block design, wherein the sub-master includes some design data about the dynamically protected block but does not by itself contain or obtain design data that are needed to construct details of an instance of the dynamically protected IP block within a boundary of the dynamically protected IP block by a parameterized cell evaluation module in an electronic circuit design tool; and

instantiating an instance the dynamically protected IP block design in the electronic circuit design by using an instance of the sub-master.

34. The article of manufacture of claim 30, further comprising:

the program code which, when executed by the at least one processor or processor core, causes the at least one processor or processor core to perform an act of preventing an access to another one of the plurality of sub-masters of the IP block design with the key.

35. The article of manufacture of claim 30, in which the program code which, when executed by the at least one processor or processor core, causes the at least one processor or processor core to perform the one or more acts comprising using the key to retrieve one of the plurality of sub-masters of the IP block design further comprises:

a segment of the program code which, when executed, causes the at least one processor or processor core to perform an act of identifying at least a portion of the side file, in which the portion is associated with the key; and

the segment of the program code which, when executed, causes the at least one processor or processor core to perform an act of performing a decryption process on the portion to retrieve the one of the plurality of sub-masters of the IP block design.

36. The article of manufacture of claim 30, further comprising:

the program code which, when executed, causes the at least one processor or processor core to perform an act of identifying a reference from the side file to a second side file, in which the second side file comprises a second actual design data for a second IP block design;

the program code which, when executed, causes the at least one processor or processor core to perform an act of using a second key to retrieve one of a second plurality of sub-masters of the second IP block design; and

the program code which, when executed, causes the at least one processor or processor core to perform an act of instantiating the second IP block design in the electronic circuit design by using a second instance of the one of the second plurality of sub-masters.