Methods, systems, and articles of manufacture for dynamic protection of intellectual property in electronic circuit designs
First Claim
1. A computer implemented method for implementing dynamic protection of intellectual property in an electronic circuit design, comprising:
- using a computer system that comprises at least one processor or process core executing one or more threads to perform a process, the process comprising;
initiating an encapsulation process for a block of electronic design;
creating a first parameterized cell instance for the block of electronic design with a first level of encryption of or access to the block of electronic design, wherein the first parameterized cell includes some design data about the block but does not by itself contain or obtain design data that are needed to construct details of the first parameterized cell instance of the block within a boundary of the block of electronic design by a parameterized cell evaluation module in an electronic circuit design tool; and
encrypting a first set of design data associated with the first level of encryption or access in a first sub-master for the first parameterized cell instance with the first level of encryption or access.
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Accused Products
Abstract
Various embodiments describe methods and systems for dynamic IP protection in electronic circuit designs. The methods or systems determine one or more levels of access or encryption and identify design data that should be made available for each level. For each level, a pcell instance is created to hide actual design data, and the design data that should be made available are moved to an instance of the corresponding sub-master in memory. The design data in this instance are encrypted in memory and are persisted in a side file in a non-volatile computer accessible storage medium. An authorized user is provided with a key, the side file, and a decrypting scheme to retrieve the actual design data with an appropriate level of details from the side file during a pcell evaluation process.
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Citations
36 Claims
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1. A computer implemented method for implementing dynamic protection of intellectual property in an electronic circuit design, comprising:
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using a computer system that comprises at least one processor or process core executing one or more threads to perform a process, the process comprising; initiating an encapsulation process for a block of electronic design; creating a first parameterized cell instance for the block of electronic design with a first level of encryption of or access to the block of electronic design, wherein the first parameterized cell includes some design data about the block but does not by itself contain or obtain design data that are needed to construct details of the first parameterized cell instance of the block within a boundary of the block of electronic design by a parameterized cell evaluation module in an electronic circuit design tool; and encrypting a first set of design data associated with the first level of encryption or access in a first sub-master for the first parameterized cell instance with the first level of encryption or access. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An article of manufacture comprising a non-transitory computer accessible storage medium having a sequence of instructions which, when executed by at least one processor or processor core executing one or more threads, causes the at least one processor or processor core to perform a method for implementing dynamic protection of intellectual property in an electronic circuit design, comprising:
a program code which, when executed by at the least one processor of a computer system, causes the at least one processor to perform one or more acts, the one or more acts comprising; initiating an encapsulation process for a block of electronic design; creating a first parameterized cell instance for the block of electronic design with a first level of encryption of or access to the block of electronic design, wherein the first parameterized cell includes some design data about the block but does not by itself contain or obtain design data that are needed to construct details of the first parameterized cell instance of the block within a boundary of the block of electronic design by a parameterized cell evaluation module in an electronic circuit design tool; and encrypting design data associated with the first level of encryption or access in a sub-master for the first parameterized cell instance with the first level of encryption or access. - View Dependent Claims (13, 14, 15, 16)
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17. A system for implementing dynamic protection of intellectual property in an electronic circuit design, comprising:
a computer system that comprises at least one processor or processor core executing one or more threads and is at least to; initiate an encapsulation process for a block of electronic design; create a first parameterized cell instance for the block of electronic design with a first level of encryption of or access to the block of electronic design, wherein the first parameterized cell includes some design data about the block but does not by itself contain or obtain design data that are needed to construct details of the first parameterized cell instance of the block within a boundary of the block of electronic design by a parameterized cell evaluation module in an electronic circuit design tool; and encrypt design data associated with the first level of encryption or access in a sub-master for the first parameterized cell instance with the first level of encryption or access. - View Dependent Claims (18, 19, 20, 21)
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22. A computer implemented method for using a dynamically protected intellectual property block design in an electronic circuit design, comprising:
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using a computer system that comprises at least one processor or process core executing one or more threads and is to perform a process, the process comprising; identifying a side file for the dynamically protected intellectual property (IP) block design; using a key to retrieve a sub-master of a plurality of sub-masters of the dynamically protected IP block design, wherein the sub-master includes some design data about the dynamically protected block but does not by itself contain or obtain design data that are needed to construct details of an instance of the dynamically protected IP block within a boundary of the dynamically protected IP block by a parameterized cell evaluation module in an electronic circuit design tool; and instantiating the instance of the dynamically protected IP block design in the electronic circuit design by using an instance of the sub-master. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A system for using a dynamically protected intellectual property block design in an electronic circuit design, comprising:
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a computer system that comprises at least one processor or process core executing one or more threads and is to; identify a side file for the dynamically protected intellectual property (IP) block design; use a key to retrieve a sub-master of a plurality of sub-masters of the dynamically protected IP block design, wherein the sub-master includes some design data about the dynamically protected block but does not by itself contain or obtain design data that are needed to construct details of an instance of the dynamically protected IP block within a boundary of the dynamically protected IP block by a parameterized cell evaluation module in an electronic circuit design tool; and initiate an instance the dynamically protected IP block design in the electronic circuit design by using an instance of the sub-master. - View Dependent Claims (31, 32, 33)
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30. An article of manufacture comprising a non-transitory computer accessible storage medium having a sequence of instructions which, when executed by at least one processor or processor core executing one or more threads, causes the at least one processor or processor core to perform a method for using a dynamically protected intellectual property block design in an electronic circuit design, the method comprising:
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a program code which, when executed by at least one processor or processor core executing one or more threads of a computer system, causes the at least one processor to perform one or more acts, the one or more acts comprising; identifying a side file for the dynamically protected intellectual property (IP) block design; using a key to retrieve a sub-master of a plurality of sub-masters of the dynamically protected IP block design, wherein the sub-master includes some design data about the dynamically protected block but does not by itself contain or obtain design data that are needed to construct details of an instance of the dynamically protected IP block within a boundary of the dynamically protected IP block by a parameterized cell evaluation module in an electronic circuit design tool; and instantiating an instance the dynamically protected IP block design in the electronic circuit design by using an instance of the sub-master. - View Dependent Claims (34, 35, 36)
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Specification