Leveraging chip variability

• US 8,977,910 B2
• Filed: 03/08/2013
• Issued: 03/10/2015
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Zorn, Benjamin, Bittner, Ray, Kirovski, Darko, Pattabiraman, Karthik
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HOANG, TRI M
• Application Number:
  US13/791,479
• Publication Number:
  US 20130205174A1
• Time in Patent Office: 732 Days
• Field of Search: 714/48
• US Class Current: 714/48
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Claims

1. A method comprising:

correlating different levels of an error-sensitive factor of a chip with errors of respective areas of the chip detected at each of the different levels, the error-sensitive factor comprising a physical trait of the chip such that a likelihood of an error occurring on the chip changes in according with changes in the level of the error-sensitive factor; and

using indicia of the detecting of errors to store area-specific error statistics, wherein the area-specific error statistics are able to map, at a given time, for each area, values of the error-sensitive factor to respective error statistics, where for any given one of the areas and any given one of the values, the area-specific error statistics are able to provide, at the given time, a corresponding error statistic that is specific to the given one of the areas and is specific to the given one of the values.

2. A method according to claim 1, further comprising using the area-specific error statistics to perform error or power management while an application uses memory comprising the chip.

3. A method according to claim 2, wherein the chip comprises a DRAM chip and using the area-specific error statistics comprises increasing use of some areas of the chip and decreasing use of other areas of the chip, or increasing or decreasing a setting of the chip that controls power consumption by the chip.

4. A method according to claim 1, further comprising receiving a current level of the error-sensitive factor, using the area-specific error statistics to obtain indicia of error expectation of areas based on the current level, computing a signature of the chip based on the indicia of error expectation, and comparing the signature with a signature from a pre-computed signature function.

5. A method according to claim 1, further comprising inducing different levels of the error-sensitive factor upon the chip and repeatedly writing data to the chip and reading data from the chip and counting an error for a particular area when data read from the particular area is determined to differ from data previously written to the particular area.

6. A method according to claim 1, wherein errors of an area are measured at the different levels of the error-sensitive factor, and a function for the area-specific error statistics comprises a level parameter such that when provided with a level value via the parameter the function obtains an error statistic for a specified area that is specific to the level value.

7. A method according to claim 1, wherein the error-sensitive factor comprises a voltage powering the chip or a frequency at which the chip operates, or a rate at which the memory is refreshed.

8. A device comprising:

a chip comprising a plurality of regions, each region having an actual error rate that varies in accordance with variation of a physical operational parameter of the chip; and

storage storing regional error information of the regions, wherein the regional error information is able to provide, for differing input values of the physical operational parameter, corresponding indicia of predicted error statistics expected for each of the regions if the chip is operated at the differing input values of the physical operational parameter, wherein, for any given one of the input values, the regional error information is able to provide, for each of the regions, indicia of predicted error statistics that correspond to the actual error rates for the regions when the chip is operated at the given input value.

9. A device according to claim 8, wherein operation of the chip is controlled according to the predicted error statistics.

10. A device according to claim 8, wherein the physical operational parameter comprises temperature, voltage, or frequency.

11. A device according to claim 8, wherein the regions are non-overlapping with respect to each other.

12. A device according to claim 8, wherein the error statistics comprise indicia of rates of errors, probabilities of errors, or counts of errors.

13. A device according to claim 8, wherein the storage is on the chip.

14. A device according to claim 8, wherein the regional error information was derived by measuring errors that occurred in the regions of the chip at different induced levels of the physical operational parameter.

15. One or more computer readable storage media storing information to enable a computing device to execute, by a processor of the computing device, an area-specific error function, the stored information comprising:

the area-specific error function, the area-specific error function operable such that when an input level of an error-sensitive factor and an input area of the chip are provided, the area-specific error function provides information indicating an error statistic that is specific to the input level and the input area, wherein the area-specific error function was derived by causing errors to occur on the chip, or on another chip, by causing the chip, or the other chip, to have different levels of the error-sensitive factor of the chip, or the other chip, and by measuring errors of respective areas of the chip, or the other chip, that occur at each of the different levels, wherein each area is measured at each of the different levels, the error-sensitive factor comprising a physical trait of the chip, or the other chip, such that a likelihood of an error occurring on the chip, or the other chip, changes in according to changes in the level of the error-sensitive factor.

16. One or more computer readable storage media according to claim 15, wherein causing the error-sensitive factor to have different levels comprises heating or cooling the chip or the other chip.

17. One or more computer readable storage media according to claim 15, wherein causing the error-sensitive factor to have different levels comprises altering a refresh rate of the chip or the other chip.

18. One or more computer readable storage media according to claim 15, wherein causing the error-sensitive factor to have different levels comprises changing a voltage level supplied to the chip or the other chip.

19. One or more computer readable storage media according to claim 15, wherein causing the error-sensitive factor to have different levels comprises changing a clock frequency of the chip or of the other chip.

20. One or more computer readable storage media according to claim 15, wherein the measuring comprises comparing data provided to the chip, or to the other chip, to be stored by the chip, or by the other chip, against data read from the chip, or from the other chip, and identifying discrepancies therebetween.