Method of early termination of channel decoding by re-encoding

• US 8,977,934 B2
• Filed: 02/04/2013
• Issued: 03/10/2015
• Est. Priority Date: 02/04/2013
• Status: Active Grant

• Current Assignee: National Tsing Hua University
• Original Assignee: National Tsing Hua University
• Inventors: Ueng, Yeong-Luh, Li, Mao Ruei
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US13/758,483
• Publication Number:
  US 20140223253A1
• Time in Patent Office: 764 Days
• Field of Search: 714/774, 714/780
• US Class Current: 714/774
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/1128 Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
• CPC Class Codes: H03M 13/2951 using iteration stopping criteria
• CPC Class Codes: H03M 13/2975 Judging correct decoding, e.g. iteration stopping criteria
• CPC Class Codes: H03M 13/3738 with judging correct decoding
• CPC Class Codes: H03M 13/3753 using iteration stopping criteria
• CPC Class Codes: H03M 13/3776 using a re-encoding step during the decoding process

Abstract

A system providing early termination for channel decoding by re-encoding including a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and to the encoding unit. Via the system, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding. Re-encoded words are compared to the decoded codewords by the checking unit and, if they are completely the same, the decoding action of the decoding unit is terminated. The system reduces power consumption and offers a simplified structure, improved decoding throughput, and reduced hardware complexity.

Claims

1. A system providing early termination for channel decoding by re-encoding at least comprising:

a decoding unit including;

a register;

a plurality of variable node units receiving incoming codewords and decoding the incoming codewords;

a plurality of check nodes units connected to the variable node units and exchanging messages therebetween; and

a hard decision connected to the variable node units so as to receive the decoded codewords and to the register so as to forward the decoded codewords and also receiving the incoming codewords,

an encoding unit connected to the hard decision, and

a checking unit connected to the hard decision, to the variable node units, to the register, and to the encoding unit, wherein decoded message words produced from the variable node units are sent to the register via the hard decision and to the encoding unit via the hard decision for re-encoding;

wherein re-encoded words are compared to decoded codewords by the checking unit; and

if they are completely the same, then decoding action of the decoding unit is terminated.

2. The system of claim 1, wherein the checking unit is a logical circuit.

3. The system of claim 1, further comprising a channel unit that is wireless, wired or other medium for transmission or storage of the incoming codewords.

4. The system of claim 1, wherein if an error correcting code is a systematic code, then it only necessary to check by the checking unit to see if parity bits after re-encoding are the same with parity bits after decoding;

and if yes, then stop decoding.

5. The system of claim 1, wherein if the comparison result of the re-encoded words and the decoded codewords is not entirely consistent, then a number of inconsistent bits is used to estimate channel signal-to-noise ratio, and the system uses this information for a corresponding action.