Organic light emitting diode display device and method of fabricating the same

• US 8,980,663 B2
• Filed: 07/18/2013
• Issued: 03/17/2015
• Est. Priority Date: 11/10/2009
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Won-Kyu, Cho, Kyu-Sik, Yang, Tae-Hoon, Choo, Byoung-Kwon, Moon, Sang-Ho, Choi, Bo-Kyung, Park, Yong-Hwan, Choi, Joon-Hoo, Shin, Min-Chul, Lee, Yun-Gyu
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US13/945,236
• Publication Number:
  US 20130302928A1
• Time in Patent Office: 607 Days
• Field of Search: 438/34, 438/158, 438/83, 438/99, 438/82, 438/725, 438/780
• US Class Current: 438/34
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/231 by etching of existing layers

Abstract

An organic light emitting diode (OLED) display device and a method of fabricating the same are disclosed. The OLED display device includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels disposed in a region in which the scan lines cross the data lines, where each pixel of the plurality of pixels includes: a switching transistor including a first gate electrode, a first semiconductor layer disposed over the first gate electrode, a first gate insulating layer interposed between the first gate electrode and the first semiconductor layer, a first source electrode and a first drain electrode, a driving transistor including a second semiconductor layer, a second gate electrode disposed over the second semiconductor layer, a second gate insulating layer interposed between the second gate electrode and the second semiconductor layer, a second source electrode and a second drain electrode, and an organic light emitting diode electrically connected with the second source and second drain electrodes of the driving transistor, where the first and second semiconductor layers are formed of the same material, and from the same processing.

Claims

1. A method of fabricating an organic light emitting diode (OLED) display device, comprising:

providing a substrate having first and second regions;

forming a first gate electrode over the first region of the substrate;

forming a first gate insulating layer over the first gate electrode;

forming a polycrystalline silicon (poly-Si) layer over the first gate insulating layer;

forming a conductive material layer over the poly-Si layer;

etching the poly-Si layer and the conductive material layer, and forming a first semiconductor layer, a first source electrode and a first drain electrode in the first region, and a second semiconductor layer, a second source electrode and a second drain electrode in the second region, wherein the first and second semiconductor layers are formed of the same material from the same processing;

forming a second gate insulating layer over the first and second source and drain electrodes;

forming a second gate electrode over the second region of the second gate insulating layer;

forming a protective layer on the second gate electrode;

etching the protective layer and the second gate insulating layer, and forming a via hole exposing one of the second source and drain electrodes; and

forming an OLED including a lower electrode electrically connected with the second source and drain electrodes through the via hole on the protective layer forming the first and second etch stop layers over and contacting at least a partial regions of the first and second semiconductor layers.

2. The method according to claim 1, further comprising crystallizing the a-Si layer into the poly-Si layer.

3. The method according to claim 1, further comprising:

forming an amorphous silicon layer over the poly-Si layer;

forming a conductive material layer over the a-Si layer; and

etching the a-Si layer doped with impurities through an etching process for the poly-Si layer and the conductive material layer, and forming a first ohmic contact layer between the first semiconductor layer and the first source and first drain electrodes, and a second ohmic contact layer between the second semiconductor layer and the second source and second drain electrodes.

4. The method according to claim 1, further comprising forming a first etch stop layer over a first region of the poly-Si layer and a second etch stop layer over a second region of the poly-Si layer.

5. The method according to claim 4, further comprising forming the first and second etch stop layers along partial regions of the first and second semiconductor layers.

6. The method according to claim 1, further comprising:

etching the second gate insulating layer and forming a first contact hole exposing one of the first source and drain electrodes; and

electrically connecting the second gate electrode with the first source and first drain electrodes through a second contact hole.

7. The method according to claim 1, further comprising:

etching the second gate insulating layer and forming a second contact hole exposing one of the second source and second drain electrodes;

forming an interconnection electrically connected with the second source and second drain electrodes through the second contact hole along with the second gate electrode; and

electrically connecting the lower electrode with the interconnection by exposing the interconnection through the via hole.

8. The method according to claim 1, further comprising forming the first and second gate electrodes using the same material and the same process.

9. The method according to claim 1, wherein the OLED is formed by forming a pixel defining layer partially exposing the lower electrode over the protective layer, forming an organic layer including one or more emission layers over the lower electrode exposed by the pixel defining layer, and forming an upper electrode over the organic layer.

10. The method according to claim 1, further comprising:

forming a planarization layer over the protective layer;

forming a via hole by etching the protective layer and the planarization layer; and

forming a lower electrode electrically connected with the second source and second drain electrodes through the via hole over the planarization layer.