Resistive memory device and method of fabricating the same

• US 8,980,721 B2
• Filed: 11/30/2012
• Issued: 03/17/2015
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Choi, Sung-Yool
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US13/690,286
• Publication Number:
  US 20130089965A1
• Time in Patent Office: 837 Days
• Field of Search: 438/382, 257/2, 365/148, 365/163
• US Class Current: 438/382
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00

Abstract

Provided are resistive memory devices and methods of fabricating the same. The resistive memory devices and the methods are advantageous for high integration because they can provide a multilayer memory cell structure. Also, the parallel conductive lines of adjacent layers do not overlap each other in the vertical direction, thus reducing errors in program/erase operations.

Claims

1. A method of fabricating a resistive memory device, comprising:

forming first conductive lines over a substrate such that the first conductive lines are parallel to each other and extend in a first direction;

forming a first data storage layer on the first conductive lines;

forming second conductive lines on the first data storage layer such that the second conductive lines are parallel to each other and extend in a second direction across the first direction;

simultaneously with the forming of the second conductive lines, forming a first oxide layer between the second conductive lines and the first data storage layer by reacting the first data storage layer with the second conductive lines;

forming a second data storage layer on the second conductive lines; and

forming third conductive lines on the second data storage layer such that the third conductive lines are parallel to each other and extend in the first direction,

simultaneously with the forming of the third conductive lines, forming a second oxide layer between the third conductive lines and the second data storage layer by reacting the second data storage layer with the third conductive lines;

wherein the third conductive line does not overlap the first conductive line in the vertical direction.

2. The method of claim 1, wherein the first and second data storage layers comprise a metal oxide layer containing a first metal.

3. The method of claim 2, wherein the second and third conductive lines comprise a second metal that has a higher oxygen affinity than the first metal of the first and second data storage layers.

4. The method of claim 1, further comprising:

forming a third data storage layer on the third conductive lines;

forming fourth conductive lines on the third data storage layer such that the fourth conductive lines are parallel to each other and extend in the second direction; and

simultaneously with the forming of the fourth conductive lines, forming a third oxide layer between the fourth conductive lines and the third data storage layer by reacting the second data storage layer with the third conductive lines,

wherein the fourth conductive line does not overlap the second conductive line in the vertical direction.

5. The method of claim 3, wherein during the forming of the second conductive lines, an oxygen of the first data storage layer is separated from the first metal of the first data storage layer and then combined with the second metal of the second conductive lines, forming a metal oxide layer at an interface between the first data storage layer and the second conductive lines.

6. The method of claim 3, wherein during the forming of the third conductive lines, an oxygen of the second data storage layer is separated from the first metal of the second data storage layer and is then combined with the second metal of the third conductive lines, forming a metal oxide layer at an interface between the second data storage layer and the third conductive lines.