Pixel structure of organic light emitting diode display

• US 8,981,350 B2
• Filed: 01/19/2011
• Issued: 03/17/2015
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Hsieh, Hsing-Hung
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US13/009,835
• Publication Number:
  US 20110248245A1
• Time in Patent Office: 1,518 Days
• Field of Search: 257/40, 257/E51.001, 257/E51.018, 438/34
• US Class Current: 257/40
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks

Abstract

A pixel structure of an organic light emitting diode display includes a first transistor and a second transistor. The first transistor includes a first drain electrode and a first source electrode. When a voltage difference is provided between the first drain electrode and the first source electrode, the first transistor has a first subthreshold slope (SS). The second transistor includes a second drain electrode and a second source electrode. When the voltage difference is provided between the second drain electrode and the second source electrode, the second transistor has a second SS, and the second SS is larger than the first SS.

Claims

1. A pixel structure of an organic light emitting diode (OLED) display, comprising:

a substrate;

a first transistor, disposed on the substrate, the first transistor being a switching transistor, and the first transistor comprising;

a first gate electrode;

an insulating layer, covering the first gate electrode and the substrate;

a first drain electrode, disposed on the insulating layer;

a first source electrode, disposed on the insulating layer;

a first channel layer, disposed on the insulating layer between the first drain electrode and the first source electrode, wherein when a voltage difference is provided between the first drain electrode and the first source electrode of the first transistor, the first transistor has a first subthreshold slope (SS); and

a first oxide layer, disposed on the first channel layer, and the first oxide layer being directly in contact with the first channel layer;

a second transistor, disposed on the substrate, the second transistor being a driving transistor, and the second transistor comprising;

a second gate electrode, disposed between the insulating layer and the substrate, the second gate electrode being electrically connected to the first drain electrode;

a second drain electrode, disposed on the insulating layer;

a second source electrode, disposed on the insulating layer; and

a second channel layer, disposed on the insulating layer between the second drain electrode and the second source electrode, wherein when the voltage difference is provided between the second drain electrode and the second source electrode of the second transistor, the second transistor has a second SS, and the second SS is larger than the first SS;

a first patterned passivation layer, covering a part of the first transistor and the second transistor, wherein the first oxide layer is disposed between the first channel layer and the first patterned passivation layer, the first patterned passivation layer is directly in contact with and covers the second channel layer, and the second channel layer and the first patterned passivation layer have no oxide layer disposed therebetween; and

an OLED, disposed on the second drain electrode and the first patterned passivation layer, wherein the second drain electrode is electrically connected to the OLED.

2. The pixel structure of claim 1, wherein a width of the first oxide layer is the same as a width of the first channel layer, and two sides of the first oxide layer are respectively aligned to two sides of the first channel layer.

3. The pixel structure of claim 1, wherein the first oxide layer is silicon oxide.

4. The pixel structure of claim 1, wherein the first channel layer and the second channel layer respectively comprise a metal oxide, polysilicon or amorphous silicon.

5. The pixel structure of claim 4, wherein the metal oxide is indium gallium zinc oxide (IGZO), indium oxide, zinc oxide or gallium oxide.

6. The pixel structure of claim 1, wherein the first channel layer is extended to be disposed between the first drain electrode and the first patterned passivation layer and between the first source electrode and the first patterned passivation layer, the first drain electrode and the first source electrode are disposed between a part of the first channel layer and the insulating layer, the second channel layer is extended to be disposed between the second drain electrode and the first patterned passivation layer and between the second source electrode and the first patterned passivation layer, and the second drain electrode and the second source electrode are disposed between a part of the second channel layer and the insulating layer.

7. The pixel structure of claim 1, wherein the first patterned passivation layer exposes a part of the second drain electrode, and the OLED comprises a transparent electrode, disposed on the second drain electrode and the first patterned passivation layer.

8. The pixel structure of claim 7, further comprising a second patterned passivation layer, and the OLED further comprising an organic light emitting layer and an electrode, wherein the second patterned passivation layer, the organic light emitting layer and the electrode are respectively disposed on the transparent electrode and the first patterned passivation layer in sequence.