Semiconductor device and field effect transistor

• US 8,981,434 B2
• Filed: 06/23/2010
• Issued: 03/17/2015
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Miyamoto, Hironobu, Okamoto, Yasuhiro, Ando, Yuji, Nakayama, Tatsuo, Inoue, Takashi, Ota, Kazuki, Endo, Kazuomi
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US13/393,002
• Publication Number:
  US 20120199889A1
• Time in Patent Office: 1,728 Days
• Field of Search: 257/76, 257/77, 257/192, 257/288
• US Class Current: 257/288
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7812 with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 29/8128 with recessed gate

Abstract

Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

Claims

1. A semiconductor device comprises:

a substrate;

a first n-type semiconductor layer;

a second n-type semiconductor layer;

a p-type semiconductor layer;

a third n-type semiconductor layer;

a drain electrode;

a source electrode; and

a gate electrode, wherein

the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer, and the third n-type semiconductor layer are laminated at the upper side of the substrate in this order,

the drain electrode is in ohmic-contact with the first n-type semiconductor layer directly or via the substrate,

the source electrode is in ohmic-contact with the third n-type semiconductor layer,

an opening portion to be filled that extends from an upper surface of the third n-type semiconductor layer to an upper part of the second n-type semiconductor layer is formed at a part of the p-type semiconductor layer and a part of the third n-type semiconductor layer,

the gate electrode is arranged so as to fill the opening portion to be filled and is in contact with an upper surface of the second n-type semiconductor layer, side surfaces of the p-type semiconductor layer, and side surfaces of the third n-type semiconductor layer at inner surfaces of the opening portion to be filled, and

the second n-type semiconductor layer has composition that changes from a drain electrode side toward a source electrode side in a direction perpendicular to a plane of the substrate and contains donor impurity

wherein the second n-type semiconductor layer has composition represented by Al_xGa_1-xN (0≦

x<

1), and a relationship between an Al composition ratio at an interface at a first n-type semiconductor layer side x₀>

0) and an Al composition interface at a p-type semiconductor layer side x_A (x_A≧

0) satisfies the following equation;

x₀>

x_A.

2. The semiconductor device according to claim 1, further comprising a gate insulation film, wherein

the gate insulation film is formed so as to cover the opening portion to be filled, and

the gate electrode is in contact with the upper surface of the second n-type semiconductor layer, the side surfaces of the p-type semiconductor layer, and the side surfaces of the third n-type semiconductor layer via the gate insulation film.

3. The semiconductor device according to claim 1, wherein at least one of the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer, and the third n-type semiconductor layer is formed of a nitride semiconductor.

4. The semiconductor device according to claim 1, wherein an Al composition ratio x of the second n-type semiconductor layer decreases continuously from x₀ to x_A from the drain electrode side toward the source electrode side in the direction perpendicular to the plane of the substrate.

5. The semiconductor device according to claim 1, wherein an Al composition ratio x of the second n-type semiconductor layer decreases in a stepwise manner from x₀ to x_A from the drain electrode side toward the source electrode side in the direction perpendicular to the plane of the substrate.

6. The semiconductor device according to claim 4, wherein a decreasing gradient of the Al composition ratio of the second n-type semiconductor layer is a steep gradient from the drain electrode side toward the source electrode side.

7. The semiconductor device according to claim 6, wherein a volume density of a polarization charge that is generated in the second n-type semiconductor layer is uniform over the entire second n-type semiconductor layer.

8. The semiconductor device according to claim 7, wherein a donor impurity concentration (m⁻

3) of the second n-type semiconductor layer is equal to a maximum value N_POL^MAX (m<sup>−

3</sup>) of a volume density of a polarization charge that can be generated in the second n-type semiconductor layer.

9. The semiconductor device according to claim 7, wherein a donor impurity concentration (m⁻

3) of the second n-type semiconductor layer is not more than 5 times a maximum value N_POL^MAX (m<sup>−

3</sup>) of a volume density of a polarization charge that can be generated in the second n-type semiconductor layer.

10. The semiconductor device according to claim 8, wherein a donor impurity concentration (m⁻

3) of the second n-type semiconductor layer is not more than 2.5 times a maximum value N_POL^MAX (m<sup>−

3</sup>) of a volume density of a polarization charge that can be generated in the second n-type semiconductor layer.

11. The semiconductor device according to claim 4, wherein a volume density of a polarization charge that is generated in the second n-type semiconductor layer decreases from the drain electrode side toward the source electrode side in the direction perpendicular to the plane of the substrate.

12. The semiconductor device according to claim 11, wherein a donor impurity concentration of the second n-type semiconductor layer decreases from the drain electrode side toward the source electrode side in the direction perpendicular to the plane of the substrate.

13. The semiconductor device according to claim 11, wherein the donor impurity concentration of the second n-type semiconductor layer is uniform over the entire second n-type semiconductor layer.

14. The semiconductor device according to claim 1, wherein the first n-type semiconductor layer and the third n-type semiconductor layer are each formed of plural n-type semiconductor layers.

15. The semiconductor device according to claim 1, wherein the opening portion to be filled is formed by removing a part of the p-type semiconductor layer and a part of the third n-type semiconductor layer.

16. The semiconductor device according to claim 1, wherein the semiconductor device is a field effect transistor.

17. The semiconductor device according to claim 1, wherein a first composition ratio at a first position of the second n-type semiconductor layer is larger than a second composition ratio at a second position of the second n-type semiconductor layer, and wherein a first distance between the first position and the drain side is smaller than a second distance between the second position and the drain side.