Source/drain contacts for non-planar transistors
First Claim
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1. A microelectronic device, comprising:
- a non-planar transistor gate over a non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers,a silicon-containing source/drain region;
at least one dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping structure;
a source/drain contact extending through a portion of the at least one dielectric material layer and comprising a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the silicon-containing source/drain region; and
a titanium silicide interface disposed between the silicon-containing source/drain region and the titanium-containing contact interface layer.
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Abstract
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
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Citations
15 Claims
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1. A microelectronic device, comprising:
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a non-planar transistor gate over a non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers, a silicon-containing source/drain region; at least one dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping structure; a source/drain contact extending through a portion of the at least one dielectric material layer and comprising a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the silicon-containing source/drain region; and a titanium silicide interface disposed between the silicon-containing source/drain region and the titanium-containing contact interface layer. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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forming a sacrificial non-planar transistor gate over a non-planar transistor fin; depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin; forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate; forming a source/drain region; removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin; forming a gate dielectric adjacent the non-planar transistor fin within the gate trench; depositing conductive gate material within the gate trench forming a capping structure within the recess; forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping structure; forming a contact opening through the at least one dielectric material to expose at least a portion of the source/drain region; conformally depositing a titanium-containing contact interface layer within the contact opening to abut the silicon-containing source/drain region; depositing a conductive contact material within the contact opening to abut the titanium-containing contact interface layer; and forming a titanium silicide interface between the silicon-containing source/drain region and the titanium-containing contact interface layer. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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Specification