Source/drain contacts for non-planar transistors

• US 8,981,435 B2
• Filed: 10/01/2011
• Issued: 03/17/2015
• Est. Priority Date: 10/01/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pradhan, Sameer S., Joshi, Subhash M., Chun, Jin-Sung
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US13/992,550
• Publication Number:
  US 20130256767A1
• Time in Patent Office: 1,263 Days
• Field of Search: 257382-384, 257/368, 257/369, 257/327, 257/347, 257/353, 257/288, 438/682, 438/683, 438/655, 438/597, 438/299, 438/197, 438/199
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02 Manufacture or treatment of semiconductor devices or of parts thereof
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Claims

1. A microelectronic device, comprising:

a non-planar transistor gate over a non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers,

a silicon-containing source/drain region;

at least one dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping structure;

a source/drain contact extending through a portion of the at least one dielectric material layer and comprising a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the silicon-containing source/drain region; and

a titanium silicide interface disposed between the silicon-containing source/drain region and the titanium-containing contact interface layer.

2. The microelectronic device of claim 1, wherein the titanium-containing contact interface layer comprises substantially pure titanium.

3. The microelectronic device of claim 1, wherein the conductive contact material comprises tungsten.

4. The microelectronic device of claim 1, wherein the titanium silicide interface resides substantially only between the silicon-containing source/drain region and the titanium-containing contact interface layer.

5. The microelectronic device of claim 1, wherein the titanium-containing contact interface layer abuts at least a portion of one non-planar transistor gate spacer.

6. The microelectronic device of claim 5, wherein the titanium-containing contact interface layer abuts at least a portion of the capping structure.

7. A method comprising:

forming a sacrificial non-planar transistor gate over a non-planar transistor fin;

depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin;

forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;

forming a source/drain region;

removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;

forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;

depositing conductive gate material within the gate trench forming a capping structure within the recess;

forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping structure;

forming a contact opening through the at least one dielectric material to expose at least a portion of the source/drain region;

conformally depositing a titanium-containing contact interface layer within the contact opening to abut the silicon-containing source/drain region;

depositing a conductive contact material within the contact opening to abut the titanium-containing contact interface layer; and

forming a titanium silicide interface between the silicon-containing source/drain region and the titanium-containing contact interface layer.

8. The method of claim 7, wherein conformally depositing the titanium-containing contact interface layer comprises conformally depositing a substantially pure titanium contact interface layer.

9. The method of claim 7, wherein depositing a conductive contact material within the contact opening comprises depositing tungsten within the contact opening.

10. The method of claim 7, wherein forming the titanium silicide interface between the silicon-containing source/drain region and the titanium-containing contact interface layer comprises forming the titanium silicide interface between the silicon-containing source/drain region and the titanium-containing contact interface layer by heating the silicon-containing source/drain region and the titanium-containing contact interface layer.

11. The method of claim 7, wherein forming the titanium silicide interface comprises forming the titanium silicide substantially only between the silicon-containing source/drain region and the titanium-containing contact interface layer.

12. The method of claim 7, wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material to expose a portion of the source/drain region and at least a portion of one non-planar transistor gate spacer.

13. The method of claim 12, wherein the forming the titanium-containing contact interface layer further comprises forming the titanium-containing contact interface layer to abut at least a portion of one non-planar transistor gate spacer.

14. The method of claim 7, wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material to expose a portion of the source/drain region and at least a portion of the capping structure.

15. The method of claim 14, wherein the forming the titanium-containing contact interface layer further comprises forming the titanium-containing contact interface layer to abut at least a portion of the capping structure.