Power semiconductor device

• US 8,981,469 B2
• Filed: 09/25/2013
• Issued: 03/17/2015
• Est. Priority Date: 05/12/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Tamaki, Tomohiro, Nakazawa, Yoshito
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): FORTICH, RODOLFO D
• Application Number:
  US14/037,103
• Publication Number:
  US 20140027842A1
• Time in Patent Office: 538 Days
• Field of Search: 257/288, 257/330, 257/332, 257/334, 257/341, 257/342, 257/409, 257/492, 257/493, 257/E29.012, 257/E29.255, 257/140, 257/77, 257/655
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Claims

1. A semiconductor device including a power MISFET having a super junction structure, comprising:

a semiconductor substrate;

an n-type layer formed over the semiconductor substrate;

first and second p-type impurity regions formed in the semiconductor substrate;

a first p-type column extending in a first direction in a plan view, formed in the n-type layer and arranged under the first p-type impurity region;

a second p-type column extending in the first direction in the plan view, formed in the n-type layer and arranged under the second p-type impurity region;

a third p-type column extending in the first direction in the plan view, formed in the n-type layer and arranged under the second p-type impurity region;

a first groove formed in the first p-type impurity region, such that a bottom of the first groove is arranged in first p-type impurity region and is arranged over the first p-type column;

a second groove formed in the second p-type impurity region, such that a bottom of the second groove is arranged in second p-type impurity region and is arranged over the second p-type column;

a first n-type impurity region formed in the first p-type impurity region and exposed at a side wall of the first groove;

a second n-type impurity region formed in the second p-type impurity region and exposed at a side wall of the second groove;

a trench gate electrode formed in the n-type layer and arranged between the first and second columns and between the first and second n-type impurity regions;

a first insulating film formed over the trench gate electrode; and

a source electrode formed over the trench gate electrode through the first insulating film, embedded in the first and second grooves, and electrically connected to the first and second p-type impurity regions and the first and second n-type impurity regions,

wherein the third p-type column is arranged between the second p-type column and an edge of the semiconductor substrate in a second direction perpendicular to the first direction in the plan view, and

wherein, in the second direction, a width of the third p-type column is larger than a width of the first p-type column and is larger than a width of the second p-type column.

2. A semiconductor device according to claim 1,

wherein no grooves, which are formed at the same time with the first and second grooves, are formed over the third p-type column.

3. A semiconductor device according to claim 1,

wherein a third p-type impurity region, whose concentration is higher than that of the first p-type impurity region, is formed in the first p-type impurity region and arranged at the bottom of the first groove, and

wherein a fourth p-type impurity region, whose concentration is higher than that of the second p-type impurity region, is formed in the second p-type impurity region and arranged at the bottom of the second groove.

4. A semiconductor device according to claim 1,

wherein a p-type RESURF region, whose concentration is lower than that of the second p-type impurity region, is formed in the n-type layer and is arranged between the second p-type impurity region and the edge of the semiconductor substrate in the second direction in the plan view.

5. A semiconductor device according to claim 4, further comprising:

a fourth p-type column extending in the first direction, formed in the n-type layer, arranged under the p-type RESURF region, and arranged between the third p-type column and the edge of the semiconductor substrate in the second direction in the plan view.

6. A semiconductor device according to claim 5, further comprising:

a guard ring made of a conductive film and arranged between the fourth p-type column and the edge of the semiconductor substrate in the second direction in the plan view.

7. A semiconductor device according to claim 1,

wherein, each of the first, second and third p-type columns has a lower portion and an upper portion of greater width than the lower portion in the second direction.

8. A semiconductor device according to claim 1,

wherein each of the first, second and third p-type columns is formed of an epitaxial silicon.